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Instructions and Addresses
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Add Unit adder address register allows architecture arithmetic unit associated Atlas Background Processor banks bits block branch buffer register bytes cache central memory central processor clock period contains Control Point copied corresponding CRAY X-MP CYBER decoded delay descriptor digit doubleword element example execution rate fetching floating-point addition floating-point unit FORTRAN functional units hardware highway IBM System/360 Increment index registers input operands Instruction Buffer instruction format instruction pipeline instruction set Instruction Stack Instruction Word involves issued length loaded logic loop machines main storage mantissa MFLOPS minor cycle Multiply Unit Mwords Name Store occurs operand accessing organisation output page fault parallel pipeline port pre-fetching processing rate PROP Register File requests result register scalar scalar processor sequence sequential stacking machine stage Store Access store word string Strobe tion updated vector instruction vector operations vector processor vector registers virtual address