Architectures and compilation techniques for fine and medium grain parallelism: proceedings of the IFIP WG 10.3 Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, Orlando, Florida, USA, 20-22 January 1993
Medium and especially fine grain parallelism has been a focus of the data-research area since its inception in the 1970's. Much experience has been gained but the interest both in the academia and the industry continues to flourish.The development of multiple ALU superscalars/superpipelined machines/VLIWs (small resources Von Neumann machines) has meant the related software and hardware topics for finding higher degrees of fine and medium grain parallelism on such machines has become increasingly important.This volume presents new parallelization ideas being discovered in this relatively unchartered research area, including some which are likely to have immediate practical impact. With invited papers from prominent specialists, it is hoped it also offers a critical review of the accomplishments of the data-flow research area to date.
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J Wang and C Eisenbeis
Efficient Execution of Doacross Loops on Distributed
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algorithm allocation analysis application arcs array assignment barrier basic block benchmarks branch buffer chain cluster code motion codeblock column-numbers Compilation Techniques computation constraints context switches cycle data dependence data tokens defined dependence graph dimension Doacross edges efficient element example execution flow Fortran from(e functional unit global hardware heuristic high performance IFIP implementation initiation interval inner loops input instruction integer interprocedural Istream width iteration mapping language latency LDDG loop body loop unrolling machine Medium Grain Parallelism memory access memory modules method microcode MIMD multiple multiprocessor multithreading nested loops node number of processors operand operations optimal output Parallel Computing Parallel Processing path permutation priority problem Proc resource requirements RGNINF RISC row-number sequence sequential simulation SISAL software pipelining speedup split-phase star graph storage hierarchy stream structure subtree superscalar synchronization thread transformation tree UNIREDI variable vector VLIW