Behavioral Synthesis and Component Reuse with VHDL

Front Cover
Springer Science & Business Media, 1997 - Computers - 263 pages
Improvement in the quality of integrated circuit designs and a designer's productivity can be achieved by a combination of two factors:
  • Using more structured design methodologies for extensive reuse of existing components and subsystems. It seems that 70% of new designs correspond to existing components that cannot be reused because of a lack of methodologies and tools.
  • Providing higher level design tools allowing to start from a higher level of abstraction. After the success and the widespread acceptance of logic and RTL synthesis, the next step is behavioral synthesis, commonly called architectural or high-level synthesis.

Behavioral Synthesis and Component Reuse with VHDL provides methods and techniques for VHDL based behavioral synthesis and component reuse. The goal is to develop VHDL modeling strategies for emerging behavioral synthesis tools. Special attention is given to structured and modular design methods allowing hierarchical behavioral specification and design reuse. The goal of this book is not to discuss behavioral synthesis in general or to discuss a specific tool but to describe the specific issues related to behavioral synthesis of VHDL description.
This book targets designers who have to use behavioral synthesis tools or who wish to discover the real possibilities of this emerging technology. The book will also be of interest to teachers and students interested to learn or to teach VHDL based behavioral synthesis.
 

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Contents

INTRODUCTION
1
ABSTRACTION LEVELS
2
13 BEHAVIORAL SYNTHESIS
5
14 DESIGN REUSE
17
15 COMPONENT REUSE IN VLSI
18
16 MODULAR DESIGN METHODOLOGY FOR COMPONENT REUSE AT THE BEHAVIORAL LEVEL
20
17 SUMMARY
22
MODELS FOR BEHAVIORAL SYNTHESIS
23
51 MAIN PRINCIPLES
154
52 DESIGN STEPS AND EXECUTION MODELS
160
53 INTERACTIVE SYNTHESIS
183
54 BEHAVIORAL SYNTHESIS IN THE DESIGN LOOP
192
55 SUMMARY
198
CASE STUDY HIERARCHICAL DESIGN USING BEHAVIORAL SYNTHESIS
201
62 SPECIFICATIONS
202
63 SYSTEMLEVEL ANALYSIS AND PARTITIONING
203

22 THE DATAPATH CONTROLLER MODEL
33
23 DATAPATH MODELS
40
24 CONTROLLER MODELS
58
25 SUMMARY
64
VHDL MODELING FOR BEHAVIORAL SYNTHESIS
67
31 INTERPRETATION OF VHDL DESCRIPTIONS
68
32 BEHAVIORAL VHDL EXECUTION MODES
89
33 SCHEDULING VHDL DESCRIPTIONS
94
34 SUMMARY
123
BEHAVIORAL VHDL DESCRIPTION STYLES FOR DESIGN REUSE
125
42 DESIGN REUSE AT THE BEHAVIORAL LEVEL
133
43 MODULAR DESIGN
139
44 VHDL MODELING FOR REUSE
142
45 TOWARDS OBJECT ORIENTED DESIGN IN VHDL
148
46 SUMMARY
152
ANATOMY OF A BEHAVIORAL SYNTHESIS SYSTEM BASED ON VHDL
153
65 DESIGN FOR REUSE OF THE FIXEDPOINT UNIT AS A BEHAVIORAL COMPONENT
204
66 ABSTRACTION FOR REUSE
207
67 DESIGN REUSE
208
68 THE BEHAVIORAL SYNTHESIS PROCESS
211
69 SUMMARY
213
CASE STUDY MODULAR DESIGN USING BEHAVIORAL SYNTHESIS
215
72 SYSTEM SPECIFICATION
216
73 SYSTEM PARTITIONING
219
74 BEHAVIORAL SPECIFICATIONS OF SUBSYSTEMS
225
75 SYSTEM DESIGN
237
76 BEHAVIORAL AND RTL SIMULATIONS
244
77 SUMMARY
245
REFERENCES
247
INDEX
259
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