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Dynamic OnChip Memory Management for Chip Multiprocessors
Reducing Energy Consumption of Queries in MemoryResident Database Systems
Low Power Processors
14 other sections not shown
algorithm application approach architecture ASIC bank benchmarks block branch predictor cache line cache miss cluster compiler components compression Computer configuration constraints core cotransformation cycles data cache design space disk drive dynamic Ehrhart polynomials embedded systems encryption energy consumption equation execution FPGA framework function units fused loop global graph Hamming distance hardware IEEE implementation input instruction cache International iteration latency leakage energy linear link utilization loop fusion mapping memory mode multiprocessor multithreaded node on-chip operation optimal output overhead packet parameters partitioning patterns performance pipeline pointer power consumption power models prefetch problem procedure real-time reduce requires retiming reuse run-time scheduling scheme Section Sherpa shown in Figure shuffle buffer simulation slice solution speed SRAM stack static StepNP sub-bank System-on-a-Chip SystemC Table task techniques thread tion topologically sorted upward cone variables vectors VLIW voltage WCET XScale XTensa