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Short Presentations with Posters I
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algorithm allocation analysis AOTC application approach architecture array basic block behavior benchmarks bits Bloom filter branch branch predictor buffer cache line CGRA compiler compiler optimizations components compression Computer configuration core cost cycle dynamic efficient embedded systems energy consumption entry evaluate execution fetch filter flash memory FPGA function graph hardware helpers IEEE implementation input instruction cache integrated International Symposium Java language latency leakage logic lookup loop mapped Microarchitecture microcontroller microhotplate nodes operations optimization output overhead packet packing parameters performance pipeline prediction predictor Proc processor proposed provides reduce register file requires runtime scheduling Section selection shown in Figure shows SIMD simulation slots SMFA soft errors software pipelining space speedup SRAM static sub-heap subgraph SystemC Table target task techniques threads tion transformations variables VLIW voltage