CPU Design: Answers to Frequently Asked Questions
Springer Science & Business Media, Dec 6, 2005 - Technology & Engineering - 236 pages
I am honored to write the foreword for Chandra Thimmannagari’s book on CPU design. Chandra’s book provides a practical overview of Microprocessor and high end ASIC design as practiced today. It is a valuable addition to the literature on CPU design, and is made possible by Chandra’s unique combination of extensive hands-on CPU design experience at companies such as AMD and Sun Microsystems and a passion for writing. Technical books related to CPU design are almost always written by researchers in academia or industry and tend to pick one area, CPU architecture/Bus architecture/ CMOS design that is the area of expertise of the author, and present that in great detail. Suchbooks are of great value to students and practitioners in that area. However, engineers working on CPU design need to develop an understanding of areas outside their own to be effective. CPU design is a multi dimensional problem and one dimensional optimization is often counterproductive.
What people are saying - Write a review
Circuits and Layout
Verification and Testing
Other editions - View all
4-Way Set Associative architectural Associative Cache Memory buffer bus to forward bus which forces byte7 Cache Coherency Caches or Main capacitive coupling Chip circuit clock domain Code Coverage cycle data from Main executed Figure below shows flop forces Main Memory forward the latest Functionality input instructions integer Invalidate local Caches Issue Queue latest data corresponding layout Load logic Main Memory Memory or foreign Mentor Graphics MHOSI Mintime MOESI netlist node Noise ofthe output Parity bit pass gate Mux path pipe stages Place and Route power dissipated provides read ports Register File register specifiers renamed request Set Associative Cache shown in Figure signal simulation sitting in entry source register Spec statement_group Static Timing Analysis strand Sun Microsystems superscalar System bus Table below shows Tag array tion Tools Tool transistor typical Update entry vector Verilog voltage Way0 WRF_ID Write Miss address write ports