CardBus system architecture
A crisply written and comprehensive set of guides to the most important PC hardware standards. Each series title explains from a programmer's perspective the architecture, features, and operation of systems built using one particular type of chip or industry-accepted hardware specification. The series features step-by-step descriptions and instructions and accessible illustrations that enable readers to easily understand difficult hardware topics. Card Bus System Architecture is a working guide to a new hardware standard.
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About This Book
16Bit PC Cards A Review
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16-bit PC Card address phase arbiter asserted base address register bridge's bus master bus number byte enables cache line CAD bus card detect card services card's CardBus bridge CardBus card CardBus devices CardBus functions CardBus Socket CCLK CDEVSEL CFRAME CGNT chapter CIRDY client driver clock cell command register configuration registers configuration software configuration transaction CPAR CPERR CRST CSERR CSTOP CSTSCHG CTRDY data item Data Parity data phase data transfer deasserted defined device driver device's doubleword Event register Figure host bus adapter implemented indicates initiator inserted interrupt pin interrupt request interrupt routing IRQ line latches locked memory read memory target memory write parity error PC Card Standard PCI bus PCI configuration PCI device PCMCIA prefetchable Present State register processor Reserved reset retry ROM image signal socket interface special cycle specified status change interrupt status register Table target device tion tuple type zero wakeup write transaction