Circuit Design with VHDL
This textbook teaches VHDL using system examples combined with programmable logic and supported by laboratory exercises. While other textbooks concentrate only on language features, Circuit Design with VHDL offers a fully integrated presentation of VHDL and design concepts by including a large number of complete design examples, illustrative circuit diagrams, a review of fundamental design concepts, fully explained solutions, and simulation results. The text presents the information concisely yet completely, discussing in detail all indispensable features of the VHDL synthesis. The book is organized in a clear progression, with the first part covering the circuit level, treating foundations of VHDL and fundamental coding, and the second part covering the system level (units that might be located in a library for code sharing, reuse, and partitioning), expanding upon the earlier chapters to discuss system coding.
Part I, "Circuit Design," examines in detail the background and coding techniques of VHDL, including code structure, data types, operators and attributes, concurrent and sequential statements and code, objects (signals, variables, and constants), design of finite state machines, and examples of additional circuit designs. Part II, "System Design," builds on the material already presented, adding elements intended mainly for library allocation; it examines packages and components, functions and procedures, and additional examples of system design. Appendixes on programmable logic devices (PLDs/FPGAs) and synthesis tools follow Part II. The book's highly original approach of teaching through extensive system examples as well as its unique integration of VHDL and design make it suitable both for use by students in computer science and electrical engineering.
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11 ARCHITECTURE 14 BEGIN 9 10 ARCHITECTURE 9 END Altera Antifuse array assignments barrel shifter BEGIN 15 BIT_VECTOR BLOCK chapter chip circuit clk'EVENT AND clk='l clock clock signal compiler CONSTANT count counter cout CPLDs data types decimal declared design style device diagram dout EEPROM ELSIF clk'EVENT encoder END COMPONENT END LOOP END PROCESS flip-flops FPGAs FUNCTION ieee.std_logic_1164.all implementation INTEGER RANGE lDxlD LIBRARY ieee logic main code MaxPlus ModelSim multiplier multiply-accumulate my_package NAND next_state Notice number of bits nx_state operators outp output parameter pins PORT MAP pr_state pre-defined presented problem PROCEDURE PROCESS clk programmable Programmable Logic Devices qbar reset results of example sequential code sequential logic seven-segment display shift register shown in figure SIGNED Simulation results solution specified statement STD_LOGIC STD_LOGIC_VECTOR 7 DOWNTO synchronous syntax temp2 tempi UNSIGNED user-defined vector VHDL code waveforms Xilinx