Code Generation for Embedded Processors
Peter Marwedel, Gert Goossens
Springer US, Jun 30, 1995 - Computers - 298 pages
Modern electronics is driven by the explosive growth of digital communications and multi-media technology. A basic challenge is to design first-time-right complex digital systems, that meet stringent constraints on performance and power dissipation.
In order to combine this growing system complexity with an increasingly short time-to-market, new system design technologies are emerging based on the paradigm of embedded programmable processors. This concept introduces modularity, flexibility and re-use in the electronic system design process. However, its success will critically depend on the availability of efficient and reliable CAD tools to design, programme and verify the functionality of embedded processors.
Recently, new research efforts emerged on the edge between software compilation and hardware synthesis, to develop high-quality code generation tools for embedded processors. Code Generation for Embedded Systems provides a survey of these new developments. Although not limited to these targets, the main emphasis is on code generation for modern DSP processors. Important themes covered by the book include: the scope of general purpose versus application-specific processors, machine code quality for embedded applications, retargetability of the code generation process, machine description formalisms, and code generation methodologies.
Code Generation for Embedded Systems is the essential introduction to this fast developing field of research for students, researchers, and practitioners alike.
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CODE GENERATION FOR EMBEDDED
CHALLENGES IN CODE GENERATION
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algorithm application approach ASIPs assignment basic block behaviour catenation CDFG Chess code selection CodeSyn compaction computed constraints core corresponding cost cycle datapath dependencies described digital signal processors DSP processors DSP-core edges efficient embedded processors embedded systems example execution expression trees functional units graph hardware implementation input instruction set simulator intermediate load loop machine description memory microcode modules move Mutation Scheduling netlist nodes normal form programs operand operations optimization output parallel path patterns performed phase pipeline ports problem program threads re-write real-time register allocation register file register set register transfers representation represented resource result retargetable code retargetable compiler Section self-test programs sequence shown in Figure specification spill SRUs structure Table target architecture target machine target processor task techniques thread frame tion transformation trellis diagrams trellis tree TTAs variables VHDL VLIW
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Retargetable Code Generation for Digital Signal Processors
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