Comprehensive Functional Verification: The Complete Industry Cycle
One of the biggest challenges in chip and system design is determining whether the hardware works correctly. That is the job of functional verification engineers and they are the audience for this comprehensive text from three top industry professionals.
As designs increase in complexity, so has the value of verification engineers within the hardware design team. In fact, the need for skilled verification engineers has grown dramatically--functional verification now consumes between 40 and 70% of a project's labor, and about half its cost. Currently there are very few books on verification for engineers, and none that cover the subject as comprehensively as this text.
A key strength of this book is that it describes the entire verification cycle and details each stage. The organization of the book follows the cycle, demonstrating how functional verification engages all aspects of the overall design effort and how individual cycle stages relate to the larger design process. Throughout the text, the authors leverage their 35 plus years experience in functional verification, providing examples and case studies, and focusing on the skills, methods, and tools needed to complete each verification task.
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abstraction algorithm array assertions behavior blocks Boolean cache Calc1 Calc2 cation Chapter checker checking components chip clock command complete constraints create debug design team design under verification drive error escape analysis event-driven example Figure formal verification functional verification FV tools hardware hardware description language ification implementation initial input instruction stream interface language latches level of verification logic memory microprocessor monitor multiple occur on-the-fly opcode OpenVera operand operation output packet performance pipeline port problem processor property specification language protocol queue random re-use reference model regression requires reset scan ring scenarios scoreboard sequence signal simulation engine specification stimulus component structure tape-out test bench test bench components tion transaction unit update valid verifica verification components verification cycle verification engineer verification environment verification plan verification team Verilog VHDL