Computer Aided Verification: 3rd International Workshop, CAV '91, Aalborg, Denmark, July 1-4, 1991. Proceedings
This volume contains the proceedings of the third International Workshop on Computer Aided Verification, CAV '91, held in Aalborg, Denmark, July 1-4, 1991. The objective of this series of workshops is to bring together researchers and practitioners interested in the development and use of methods, tools and theories for automatic verification of (finite) state systems. The workshop provides a unique opportunity for comparing the numerous verification methods and associated verification tools, and the extent to which they may be utilized in application design. The emphasis is not only on new research results but also on the application of existing results to real verification problems. The papers in the volume areorganized into sections on equivalence checking, model checking, applications, tools for process algebras, the state explosion problem, symbolic model checking, verification and transformation techniques, higher order logic, partial order approaches, hardware verification, timed specification and verification, and automata.
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abstract actions algorithm applied assertion automata automated Automatic Verification automaton axioms behavior Biichi binary decision diagrams bisimilar bisimulation bisimulation equivalence block boolean branching bisimulation buffers cache calculus circuit components Computer Science concurrent systems construction correctness corresponding covering graph defined definition denote described deterministic E.M. Clarke environment equations example execution expression finite Formal formal verification formula function given hardware higher-order logic HMS machines implementation induction infinite initial input Kripke structure labeled transition system language lemma LNCS Lotos memory model checking node operational semantics output paper parallel composition perform Petri nets prefix problem Proc process algebra proof Proposition protocol queue reachable recursive refusal sets represent restriction result safety properties satisfies sequence sequential machine simulation preorder simulation relations specification subset symbolic model checking synchronous t-expressions techniques temporal logic theorem proving tpred transition relation variables vector