Computer Architecture: Software Aspects, Coding, and Hardware
With the new developments in computer architecture, fairly recent publications can quickly become outdated. Computer Architecture: Software Aspects, Coding, and Hardware takes a modern approach. This comprehensive, practical text provides that critical understanding of a central processor by clearly detailing fundamentals, and cutting edge design features. With its balanced software/hardware perspective and its description of Pentium processors, the book allows readers to acquire practical PC software experience. The text presents a foundation-level set of ideas, design concepts, and applications that fully meet the requirements of computer organization and architecture courses.
The book features a "bottom up" computer design approach, based upon the author's thirty years experience in both academe and industry. By combining computer engineering with electrical engineering, the author describes how logic circuits are designed in a CPU. The extensive coverage of a micprogrammed CPU and new processor design features gives the insight of current computer development.
Computer Architecture: Software Aspects, Coding, and Hardware presents a comprehensive review of the subject, from beginner to advanced levels. Topics include:
o Two's complement numbers o Integer overflow
o Exponent overflow and underflow o Looping
o Addressing modes o Indexing
o Subroutine linking o I/O structures
o Memory mapped I/O o Cycle stealing
o Interrupts o Multitasking
o Microprogrammed CPU o Multiplication tree
o Instruction queue o Multimedia instructions
o Instruction cache o Virtual memory
o Data cache o Alpha chip
o Interprocessor communications o Branch prediction
o Speculative loading o Register stack
o JAVA virtual machine o Stack machine principles
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16 bits 32 bits addressing mode arithmetic ASCII assembly assembly language base address biased exponent binary block byte carry output Code image complement conditional branch contains data bus data cache decimal decoded defined digit disk divide divisor eight-bit ENDDO ENDIF entry example execution fetch field flag floating point four-bit function hardware hardware register I/O processor index register instruction queue integer interpreter interrupt load logical loop M[RA means memory address memory cycle memory direct microcode microinstruction mov ax multiply negative notation offset opcode operation Pentium positional notation postfix notation program counter push result retrieval routine shift shown in Figure sign bit signal significand sopd2 source operand specified stack machine statement status register string subroutine subtract symbol target instruction target machine tion unit unsigned word zero
Page 11 - ANSI American National Standards Institute ASCII American Standard Code for Information Interchange...
Page 407 - A VLIW Architecture for a Trace Scheduling Compiler," Proc. 2nd Int. Conf. Architectural Support for Programming Languages and Operating Systems fASPLOSW,pp.l80-192,Oct. 1987. [FisherSl ] JA Fisher, "Trace Scheduling: A Technique for Global Microcode Compaction,