Computer Architecture: Software Aspects, Coding, and Hardware

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CRC Press, Dec 19, 2017 - Computers - 456 pages
With the new developments in computer architecture, fairly recent publications can quickly become outdated. Computer Architecture: Software Aspects, Coding, and Hardware takes a modern approach. This comprehensive, practical text provides that critical understanding of a central processor by clearly detailing fundamentals, and cutting edge design features. With its balanced software/hardware perspective and its description of Pentium processors, the book allows readers to acquire practical PC software experience. The text presents a foundation-level set of ideas, design concepts, and applications that fully meet the requirements of computer organization and architecture courses.

The book features a "bottom up" computer design approach, based upon the author's thirty years experience in both academe and industry. By combining computer engineering with electrical engineering, the author describes how logic circuits are designed in a CPU. The extensive coverage of a micprogrammed CPU and new processor design features gives the insight of current computer development.

Computer Architecture: Software Aspects, Coding, and Hardware presents a comprehensive review of the subject, from beginner to advanced levels. Topics include:


o Two's complement numbers o Integer overflow
o Exponent overflow and underflow o Looping
o Addressing modes o Indexing
o Subroutine linking o I/O structures
o Memory mapped I/O o Cycle stealing
o Interrupts o Multitasking
o Microprogrammed CPU o Multiplication tree
o Instruction queue o Multimedia instructions
o Instruction cache o Virtual memory
o Data cache o Alpha chip
o Interprocessor communications o Branch prediction
o Speculative loading o Register stack
o JAVA virtual machine o Stack machine principles
 

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Contents

I
11
II
11
III
11
IV
16
V
24
VI
25
VII
28
VIII
33
XLVIII
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XLIX
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L
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LI
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LII
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LIII
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LIV
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LV
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IX
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XXX
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XXXVIII
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XLI
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LXV
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LXX
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LXXI
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LXXIII
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LXXIV
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LXXVI
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LXXVII
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LXXVIII
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LXXIX
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LXXX
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LXXXI
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LXXXIV
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LXXXV
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LXXXVI
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LXXXVII
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LXXXVIII
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LXXXIX
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XC
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XCI
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XCIV
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XCV
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Page 11 - ANSI American National Standards Institute ASCII American Standard Code for Information Interchange...
Page 11 - NBS National Bureau of Standards NIST National Institute of Standards and Technology...
Page 407 - A VLIW Architecture for a Trace Scheduling Compiler," Proc. 2nd Int. Conf. Architectural Support for Programming Languages and Operating Systems fASPLOSW,pp.l80-192,Oct. 1987. [FisherSl ] JA Fisher, "Trace Scheduling: A Technique for Global Microcode Compaction,
Page 407 - Deitel, HM and Deitel, PJ, Java: How to Program, Prentice-Hall, Englewood Cliffs, NJ, 1997.

About the author (2017)

John Y. Hsu earned his Ph.D. in computer engineering at the University of California, Berkeley. Dr. Hsu is professor of computer engineering, California Polytechnic State University. He has served as a consultant to Federal Electric/ITT, IBM, and other major corporations.

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