Computer Architecture: A Quantitative Approach

Front Cover
Elsevier, Oct 7, 2011 - Computers - 856 pages
3 Reviews
Computer Architecture: A Quantitative Approach explores the ways that software and technology in the cloud are accessed by digital media, such as cell phones, computers, tablets, and other mobile devices. The book became a part of Intel's 2012 recommended reading list for developers, and it covers the revolution of mobile computing. The text also highlights the two most important factors in architecture today: parallelism and memory hierarchy.

The six chapters that this book is composed of follow a consistent framework: explanation of the ideas in each chapter; a ""crosscutting issues"" section, which presents how the concepts covered in one chapter connect with those given in other chapters; a ""putting it all together"" section that links these concepts by discussing how they are applied in real machine; and detailed examples of misunderstandings and architectural traps commonly encountered by developers and architects.

The first chapter of the book includes formulas for energy, static and dynamic power, integrated circuit costs, reliability, and availability. Chapter 2 discusses memory hierarchy and includes discussions about virtual machines, SRAM and DRAM technologies, and new material on Flash memory. The third chapter covers the exploitation of instruction-level parallelism in high-performance processors, superscalar execution, dynamic scheduling and multithreading, followed by an introduction to vector architectures in the fourth chapter. Chapters 5 and 6 describe multicore processors and warehouse-scale computers (WSCs), respectively.

This book is an important reference for computer architects, programmers, application developers, compiler and system software developers, computer system designers and application developers.

  • Part of Intel's 2012 Recommended Reading List for Developers
  • Updated to cover the mobile computing revolution
  • Emphasizes the two most important topics in architecture today: memory hierarchy and parallelism in all its forms.
  • Develops common themes throughout each chapter: power, performance, cost, dependability, protection, programming models, and emerging trends ("What's Next")
  • Includes three review appendices in the printed text. Additional reference appendices are available online.
  • Includes updated Case Studies and completely new exercises.
 

What people are saying - Write a review

User Review - Flag as inappropriate

This book is horrible. It is a book with so much of ambiguities and mistakes. Many of the solved problems are wrongly calculated. The simple maths described in many solved examples is dreadfully incorrect.
Also, the exercises at the end of the chapters seems like out of the book concepts. One cannot solve the problems by reading the chapter. It seems the people who wrote the problems didn't read the book at all. They are too many assumptions that have to be considered before solving. The exercises in the book can have different solutions and still can be confusing. Its the worst computer organisation book I have ever owned.
Hennessy and Patterson may be good researchers, but they got totally disconnected with the readers and learners by this book.
HATED THE BOOK TO THE CORE. I AM VERY DISAPPOINTED THAT I PAYED SOME AMOUNT OF MONEY TO THE AUTHORS FOR THIS PIECE OF GARBAGE.
 

User Review - Flag as inappropriate

This is a great book. I purchased without hesitation.
However, the google play version is much more expensive than a paper version, which is hard to believe.
Also, the new edition has some typos
or errors. Unfortunately, some errors in Chapter 5 ( cache coherence) cost me few hours to understand what they really mean.
Besides, I hope online appendix can be put into the google play version.
 

Contents

1 Fundamentals of Quantitative Design and Analysis
1
2 Memory Hierarchy Design
71
3 InstructionLevel Parallelism and Its Exploitation
147
4 DataLevel Parallelism in Vector SIMD and GPU Architectures
261
5 ThreadLevel Parallelism
343
6 WarehouseScale Computers to Exploit RequestLevel and DataLevel Parallelism
431
Appendix A Instruction Set Principles
A-1
Appendix B Review of Memory Hierarchy
B-1
Basic and Intermediate Concepts
C-1
References
R-1
Index
I-1
Translation between GPU terms in book and official NVIDIA and OpenCL terms
I-90
Copyright

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About the author (2011)

David A. Patterson has been teaching computer architecture at the University of California, Berkeley, since joining the faculty in 1977, where he holds the Pardee Chair of Computer Science. His teaching has been honored by the Distinguished Teaching Award from the University of California, the Karlstrom Award from ACM, and the Mulligan Education Medal and Undergraduate Teaching Award from IEEE. Patterson received the IEEE Technical Achievement Award and the ACM Eckert-Mauchly Award for contributions to RISC, and he shared the IEEE Johnson Information Storage Award for contributions to RAID. He also shared the IEEE John von Neumann Medal and the C & C Prize with John Hennessy. Like his co-author, Patterson is a Fellow of the American Academy of Arts and Sciences, the Computer History Museum, ACM, and IEEE, and he was elected to the National Academy of Engineering, the National Academy of Sciences, and the Silicon Valley Engineering Hall of Fame. He served on the Information Technology Advisory Committee to the U.S. President, as chair of the CS division in the Berkeley EECS department, as chair of the Computing Research Association, and as President of ACM. This record led to Distinguished Service Awards from ACM, CRA, and SIGARCH.

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