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DESIGN METHODOLOGY AND DESCRIPTIVE TOOLS
SYSTEM STRUCTURE THE PUS LEVEL
THE MEMORY HIERARCHY
13 other sections not shown
alternatives approach architect argument arithmetic array assembly language binary bits block buffer bytes cache memory central processor Chapter clock communication components computer architecture computer system concurrently connected cost cycle data structures DECODE described disk files evaluation example fetch-execute cycle Figure floating-point format function units general-purpose hardware identify IEEE ILLIAC IV implemented included input input/output input/output control instruction set instruction-set processor integer Intel interface interrupt large number logic machine mantissa memory modules microprocessor microprogrammed multiple multiprocessor needed operating system operating-system organization output parallel performance peripheral devices pipeline pointer primary memory problems processing processor registers programming languages queue radar random-access memory result RISC scalar secondary memory segment semiconductor sequence shown in Fig signal SIMD special-purpose specific stack storage subsystem switch synchronization transfer Unisys vector vector processors virtual memory word