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PARALLELISM WITH A SINGLE INSTRUCTION STREAM
PARALLELISM BY MESSAGE PASSING
SHARED RESOURCE SYNCHRONIZATION
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access attempt access control access control list access rights algorithm barrel basic behavior block buffer cache capability channel complete components computation condition constraints contains control unit coprocessor copy covert channel cycle data flow system deadlock described descriptor device discretionary access controls discuss entry event Example executing process feasible schedule Figure function graph hardware ILLIAC IV illustrates implementation input input/output integer interactions interprocess lock logic loop matrix merge module message passing monitor Multics operand operation options output overlapped parallel parameters path perform pipeline port problem procedure processor processor registers queue receive region request result ring numbers rules scheme security attributes security level segment semaphore sequence shared objects shared resources signal single specified structure synchronization system design system's security systolic array tag value techniques tion token transaction tree traversal vector waiting write