Computer Architecture: Design and Performance
A book aimed at design techniques used to improve the performance of computer systems. A fully revised second edition is divided into three parts; Part I describes the fundamental methods used to improve the performance of computer systems, Part II describes multiprocessor systems using shared memory and Part III includes computer systems not using shared memory. The book has complete chapters on major topics such as cache memory design, single bus multiprocessors, Interconnection networks and other techniques involving the use of parallelism. Senior/graduate level computer science, computer engineering and electrical engineering students.
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Instruction set design
Cache memory systems
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alternative arbitration architecture arithmetic array bandwidth branch instruction buffer bus master buses bytes cache memory Chapter computer system condition code register connected control unit critical section crossbar switch cycle daisy chain dataflow decoded dependency destination example execute unit fetch unit first-in first-out floating point function grant signal hardware Hence hypercube implemented input input/output instruction fetch instruction format instruction pipeline instruction set Intel interconnection network latency loaded logic loop machine instruction main memory mechanism memory access memory address memory location memory modules message-passing microprocessor microprogrammed multiprocessor multiprocessor systems node normally opcode operand operation output packet page fault parallel path performed pipeline pointer priority processing elements program counter queue real address register file replacement algorithm reservation table result RISC routing segment sequence sequential shared memory shown in Figure simultaneously specified stage stored superscalar tion token transfer variable vector virtual address write