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Cache memory systems
Reduced instruction set computers
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arbitration architecture arithmetic array average access bandwidth block branch instruction buffer bus grant bus master bus request bus system buses bytes cache computer system connected coprocessor counter critical section cross-bar switch current bus master cycle daisy chain dataflow dataflow languages Decode disk example executed first-in first-out floating point function grant signal hardware Hence hypercube identified implemented input input/output instruction fetch instruction pipeline interleaving logic loop main memory mechanism memory locations memory modules memory system message-passing microprocessor microprogrammed multiprocessor systems node number of processors operand output page fault page table parallel performed pipeline pointer priority processing elements processor registers queue real address referenced replacement algorithm reservation table RISC scheme secondary memory segment selected sequence sequential shared memory shown in Figure significant bits SIMD simultaneously specified speed-up stage static stored synchronous token transfer transputer variable virtual address virtual memory system