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THE DATAFLOW STYLE
APPEHDIX The Logic of Formal Verification
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adder algorithm architectural body architecture description language array assignment statement axiomatic Barbacci branch buffer cache Chapter CHDLs clock period compaction compiler components computer architecture Consider construct crossbar switch Dasgupta data dependency data flow data types defined denotes described description language discussed EADDR entity example execution exo-architecture fetch firmware formal functional units Gantt chart hardware description hardware description language hazard high-level host machine IDECODE IEEE implementation input instruction pipeline instruction stream interface ISPS issues latch logic loop main memory memory modules micro-architecture micro-operations microcode microcycles microinstruction microprogramming microprogramming language multiprocessor operand operation output parallel particular performance phase pipeline system postcondition problem programming language proof rule scalar Section semantics sequence sequential shifter shown in Figure simulation specification stage style switch synchronization task taxon TEST-AND-SET tion token variable vector processors verification VHDL