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Advanced Microprocessors and HighLevel
Reduced Instruction Set Computer
Computer Design for Gallium Arsenide
9 other sections not shown
algorithm allocation applications array Berkeley RISC branch broadcast cache cells cessor chip CISC compiler complex Computer Architecture computer systems connected Cosmic Cube Cray Cray X-MP Cube cycle dataflow graph delay detection distributed dynamic efficient error evaluation example execution fault fault-tolerant fetch functional programming GaAs processor global hardware IEEE IEEE Computer IEEE Trans implementation input instruction pipeline instruction set interconnection network iteration language load logic machine memory access memory modules method microcode MIMD MIPS multiple multiprocessor node operand operating system optimal output parallel computer Parallel Processing parameters partitioning path performance pipeline problem Proc processing elements queue reduce redundancy register file resource result routing tag scheduling scheme sequence shown in Figure silicon SIMD speed stage STARAN stored structure subnetwork supercomputers switch synchronization systolic systolic array task techniques transistors variable vector VLSI window