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Mainframes Workhorses of the 1960s and 1970s
Case Study 2 CDC 6600 and Cyber Series Architecture
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32 bits activation record address register address space addressing modes architects architecture arithmetic base register block branch buffers Burroughs byte cache called procedure clock cycle control registers control unit control word coprocessor Cray Research Cray X-MP datatypes decoding descriptor device effective address elements emulate execution fetch field FIGURE flag floating-point functional units general-purpose registers hardware hypercube IBM RISC System/6000 IBM System/360 ILLIAC ILLIAC IV implement index register instruction set instruction unit integer Intel interrupt logical main memory mask microinstruction microprocessor Model 91 Motorola Multiply offset operand operating system parameters perform physical address pipeline PPUs privilege level program counter queue register holds register set result register RISC router nodes S-memory scalar segment register segment table shift specified storage supercomputers tion transfer vector instructions vector operations vector processor vector registers virtual memory