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Error Tolerant Arithmetic 1
Generalized Parity Checking 3
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7th Symposium addition arithmetic operations arithmetic unit array base binary numbers block carry lookahead adder carry-lookahead carry-save carry-save adder cell chip CMOS Computer Arithmetic conversion critical path cycle denormalized digit on-line division divisor Electronics Engineering Ercegovac error detection exponent fixed-slash number floating point floating-point number floating-slash format fraction full adder function gate Hamming codes hardware IEEE Trans IEEE Transactions implementation input integer irreducible fraction iteration Japan layout logic lookahead mantissa modulo multiplier NMOS normalized number system on-line algorithms on-line arithmetic on-line delay one's complement operands optimal output overflow parallel parity check partial product partial remainder performed pipeline precision Proc Proceedings processor radix range redundant binary residue Residue Number Systems result rounding scheme shift shown in Fig signed-digit representation significand significant subtraction Symposium on Computer Table Theorem tion Transactions on Computers two's complement underflow VLSI zero