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The Map Method for Synthesis of Combinational Logic Circuits
Minimization of Boolean Functions
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39 steps addition algebra algorithm arithmetic unit assignment asynchronous circuits basis rows binary point bits Boolean Boolean algebra cache carry propagate carry-save adders column complement considered contains CORDIC corresponding counters cycle d-terms decoding delay elements described diagram dividend division divisor equations equivalent example execution flip-flop floating-point flow table full adder function gated Hence high-order hindrance instruction intersection iteration logic low-order machine matrix memory ment method minimum sum multiplicand multiplier number system obtained operands operation output p-squares pair parallel partial product partition list performed position possible prime implicant table problem procedure processing element processor pulse quotient reduced relay residue number residue number system result ripple-carry adder sector Selectrons sequence sequential sequential circuit shift shown in Fig sign digit stage step subtraction synchronous theorem tion transition two's complement variables x-change xxxx xxxx xxxx zero