Computer hardware description languages and their applications: proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications - CHDL'93 sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC, Ottawa, Ontario, Canada, 26-28 April, 1993
Hardware description languages (HDLs) have established themselves as one of the principal means of designing electronic systems. The interest in and usage of HDLs continues to spread rapidly, driven by the increasing complexity of systems, the growth of HDL-driven synthesis, the research on formal design methods and many other related advances.This research-oriented publication aims to make a strong contribution to further developments in the field. The following topics are explored in depth: BDD-based system design and analysis; system level formal verification; formal reasoning on hardware; languages for protocol specification; VHDL; HDL-based design methods; high level synthesis; and text/graphical HDLs. There are short papers covering advanced design capture and recent work in high level synthesis and formal verification. In addition, several invited presentations on key issues discuss and summarize recent advances in real time system design, automatic verification of sequential circuits and languages for protocol specification.
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Verification of the Futurebus+ Cache Coherence Protocol
Exploiting Symbolic Traversal Techniques for Efficient Process Algebra Manipulation
Hardware Verification using First Order BDDs
22 other sections not shown
abstract adder algorithm architecture array attribute automatically behavior binary decision diagrams bisimulation Bitsn boolean Boyer-Moore bv-to-nat cache cache coherence Camposano circuit Claesen clock communication communication protocols components Computer Hardware Description concepts conceptual graphs concurrent constraints data-path defined definition described Design Automation Conference diagram entity environment equivalence evaluation event example execution expression finite state machines formal verification function gate Hardware Description Languages hierarchical high-level IEEE IFIP implementation initial input integrated interaction interface internal Keywords lessOut logic logic synthesis LOTOS machine methodology methods model checking module node object operations output parameters performance port processor proof protocol prover recursive relation represent representation result rewrite rules scalarset semantics sequential shown in Figure signal simulation specification statement structure synchronization system-level systolic systolic array theorem transition UDL/I variable VHDL VLSI vVHDL