Computer Hardware Description Languages and Their Applications: Proceedings of the IFIP WG 10.2 Ninth International Symposium on Computer Hardware Description Languages and Their Applications, Washington, DC, U.S.A., 19-21 June, 1989
John A. Darringer, F. J. Rammig
North-Holland, 1990 - Technology & Engineering - 361 pages
Languages for precisely describing the behavior of computers have been studied since the conception of the computer itself. As the computer industry has grown, so has the need to exchange information about computers. Computer Hardware Description Languages (CHDL) are required to: - provide specifications and detailed implementation for a growing menu of sophisticated design automation tools, including synthesis, verification, simulation, analysis, optimization, placement, wiring and testing - communicate requirements and capabilities between suppliers and users of computer components and subsystems - facilitate the transfer of new methods and results within the university and industrial research community. As reflected in this book, there is an increased emphasis on applications and resulting requirements that are placed on CHDLs. In the field of synthesis, a major application area, there is today a focus on high-level synthesis and synthesis under design constraints. In the area of design correctness, research has shifted away from simulation to formal verification techniques such as temporal logic.
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abstraction adder algorithm allows architecture description assignment basic boolean Camposano CAR CMD cell CHDL CIRCAL circuit clock phases compiler complex components computer architectures Computer Hardware Description constraint constructs cycle Dacapo data path defined described design process design representation design tools developed devices diagram DOUT downto e-free RTL example execution EXEL expression fault fault coverage Figure finite state machines formal formal verification function gate graph Hardware Description Languages IEEE IFIP implementation input instantiation instruction integration interface interval temporal logic loop mapping memory method micro-operation model checking module Moore machine netlist node objects operand operations optimization output partition performed pipelined port primitive Proc procedure processor programming language protocol Rammig represent RISC scheduling semantics sequence signal simulation specification statement step structure model sub-environment synchronous synthesis system temporal logic formulas transformation transition variables verification VHDL VLSI