## Considerations of computation delay in the design of digital compensators for sampled-data control systems |

### What people are saying - Write a review

We haven't found any reviews in the usual places.

### Common terms and phrases

analogue computer assumed Bilinear Transform block A(nT block diagram capacitor complementary switches computation delay computer results contain delay unit Delayed Sampler digital compensator digital computer e(nT equation 46 error at sampling example of section Figure 12 Figure 20 Figure 9 finite number Hence hT seconds impulse insure intersample ripple milliseconds multivibrator number of error number of terms operate with period operational amplifiers oscillation physically realizable plant-plus-delay approach poles of G(z polynomial previous compensator outputs problem of computation pulse transfer function recent error sample Reference relaxation oscillator relay coil represents response sample and hold sampler duration sampling instants sampling period sampling switches scheme servomechanism shown in Figure simulation staggered-sampling approach steady state error step input switch closes switches are closed synthesis procedure system error system of Figure system output test input thesis unijunction transistor unit circle variable volts We(z yields z-transformations zero steady Zero-Order Hold Circuit zeros of D(z