Cryptographic Hardware and Embedded Systems -- CHES 2003: 5th International Workshop, Cologne, Germany, September 8-10, 2003, Proceedings, Volume 5
These are the proceedings of CHES 2003, the ?fth workshop on Cryptographic HardwareandEmbeddedSystems,heldinCologneonSeptember8–10,2003.As with every previous workshop, there was a record number of submissions despite themuchearlierdeadlineinthisyear'scallforpapers.Thisisaclearindication of the growing international importance of the scope of the conference and the relevance of the subject material to both industry and academia. The increasing competition for presenting at the conference has led to many excellent papers and a higher standard overall. From the 111 submissions, time constraintsmeantthatonly32couldbeaccepted.Theprogramcommitteewo- ed very hard to select the best. However, at the end of the review process there were a number of good papers – which it would like to have included but for which, sadly, there was insu?cient space. In addition to the accepted papers appearing in this volume, there were three invited presentations from Hans D- bertin (Ruhr-Universit¨ at Bochum, Germany), Adi Shamir (Weizmann Institute, Israel), and Frank Stajano (University of Cambridge, UK), and a panel d- cussion on the e?ectiveness of current hardware and software countermeasures against side channel leakage in embedded cryptosystems.
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addition adversary algorithm applied architecture binary block ciphers bytes cache misses CHES ciphertext circuit clock cycles Computer Science countermeasures cryptanalysis cryptographic Cryptographic Hardware decryption DeKaRT device Differential Power Analysis distribution divisor efficient elliptic curve Embedded Systems encryption equation exponentiation extractor fault finite field finite state machine FPGA function Gauss period Goubin’s Hardware and Embedded HECC Hidden Markov Models hyperelliptic curves IEEE implementation input integer inverse key bits key schedule leakage Lecture Notes linear LNCS logic masking matrix method MixColumns modular multiplication modulo Notes in Computer operations optimal output parameters parity performance plaintext polynomial power consumption power-analysis attacks processor proposed public key random number Rijndael round key S-box scalar multiplication scheme secret key side channel attacks signals signature smart cards Springer-Verlag standard step Table technique vector XOR gates