Cryptographic Hardware and Embedded Systems - CHES 2007: 9th International Workshop, Vienna, Austria, September 10-13, 2007, Proceedings

Front Cover
Springer Science & Business Media, Aug 28, 2007 - Business & Economics - 468 pages
CHES2007,theninthworkshoponCryptographicHardwareandEmbeddedS- tems, was sponsored by the International Association for Cryptologic Research (IACR) and held in Vienna, Austria, September 10–13, 2007. The workshop - ceived 99 submissions from 24 countries, of which the Program Committee (39 members from 15 countries) selected 31 for presentation. For the ?rst time in the history of CHES, each submission was reviewed by at least four reviewers instead of three (and at least ?ve for submissions by PC members, those now being limited to two per member) and many submitted papers have received plenty of extra reviews (some papers received up to nine reviews), thus totalling the unprecedented record of 483 reviews overall. Thepaperscollectedinthisvolumerepresentcutting-edgeworldwideresearch in the rapidly evolving ?elds of crypto-hardware, fault-based and side-channel cryptanalysis, and embedded cryptography, at the crossing of academic and - dustrial research. The wide diversity of subjects appearing in these proceedings covers virtually all related areas and shows our e?orts to extend the scope of CHES more than usual. Although a relatively young workshop, CHES is now ?rmlyestablishedasascienti?ceventofreferenceappreciatedbymoreandmore renowned experts of theory and practice: many high-quality works were subm- ted, all of which, sadly, could not be accepted. Selecting from so many good worksis no easy task and our deepest thanks go to the members of the Program Committee for their involvement, excellence, and team spirit. We are grateful to the numerous external reviewers listed below for their expertise and assistance in our deliberations.
 

What people are saying - Write a review

We haven't found any reviews in the usual places.

Contents

A FirstOrder DPA Attack Against AES in Counter Mode with Unknown Initial Counter
1
Gaussian Mixture Models for HigherOrder Side Channel Analysis
14
Side Channel Cryptanalysis of a Higher Order Masking Scheme
28
HighSpeed True Random Number Generation with Logic Gates Only
45
Protection
63
Evaluation of the Masked Logic Style MDPL on a Prototype Chip
81
Masking and DualRail Logic Dont Add Up
95
DPAResistance Without Routing Constraints?
107
FPGA Design of Selfcertified Signature Verification on Koblitz Curves
256
How to Maximize the Potential of FPGA Resources for Modular Exponentiation
272
A LowCost Parallelizable Tree for Efficient Defense Against Memory Replay Attacks
289
Power Analysis Resistant AES Implementation with Instruction Set Extensions
303
Power and EM Attacks on Passive 1356 MHz RFID Devices
320
How to Prevent from Eavesdropping on the Communication?
334
RadioFrequency Certificates of Authenticity
346
An FPGA Implementation of the Sieving Step in the Number Field Sieve Method
364

On the Power of Bitslice Implementation on Intel Core2 Processor
121
Highly Regular RighttoLeft Algorithms for Scalar Multiplication
135
A Compression Function with Reduced Hardware Requirements
148
Collision Attacks on AESBased MAC AlphaMAC
166
Secret External Encodings Do Not Prevent Transient Fault Analysis
181
Two New Techniques of SideChannel Cryptanalysis
195
AES Encryption Implementation and Analysis on Commodity Graphics Processing Units
209
Multigigabit GCMAES Architecture Optimized for FPGAs
227
Arithmetic Operators for PairingBased Cryptography
239
Collision Search for Elliptic Curve Discrete Logarithm over GF2𝑚with FPGA
378
A HardwareAssisted Realtime Attack on A52 Without Precomputations
394
Differential Behavioral Analysis
413
Information Theoretic Evaluation of SideChannel Resistant Logic Styles
427
On the Implementation of a Fast Prime Generation Algorithm
443
An UltraLightweight Block Cipher
450
Author Index
467
Copyright

Common terms and phrases