Cryptographic Hardware and Embedded Systems - CHES 2006: 8th International Workshop, Yokohama, Japan, October 10-13, 2006, Proceedings

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Springer Science & Business Media, Sep 27, 2006 - Business & Economics - 462 pages
These are the proceedings of the Eighth Workshop on Cryptographic Hardware and Embedded Systems (CHES 2006) held in Yokohama, Japan, October 10-13, 2006. The CHES workshophas been sponsored by the International Association for Cryptographic Research (IACR) since 2004. The ?rst and the second CHES workshops were held in Worcester in 1999 and 2000, respectively, followed by Paris in 2001, San Francisco Bay Area in 2002, Cologne in 2003, Boston in 2004 and Edinburgh in 2005. This is the ?rst CHES workshop held in Asia. This year,a totalof 112 paper submissionswerereceived.The reviewprocess was therefore a delicate and challenging task for the Program Committee m- bers. Each paper was carefully read by at least three reviewers, and submissions with a Program Committee member as a (co-)author by at least ?ve reviewers. The review process concluded with a two week Web discussion process which resulted in 32 papers being selected for presentation. Unfortunately, there were a number of good papers that could not be included in the program due to a lack of space. We would like to thank all the authors who submitted papers to CHES 2006. In addition to regular presentations, we were very fortunate to have in the programthreeexcellentinvitedtalksgivenbyKazumaroAoki(NTT)on“Integer Factoring Utilizing PC Cluster,” Ari Juels (RSA Labs) on “The Outer Limits of RFID Security” and Ahmad Sadeghi (Ruhr University Bochum) on “Challenges for Trusted Computing.” The program also included a rump session, chaired by Christof Paar, featuring informal presentations on recent results.
 

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Contents

hannels
1
s vs Stochastic Methods
15
ikt Gierlichs Kerstin LemkeRust Christof Paar
30
asources
46
Talk I
60
ng the SideChannel Leakage of Masked AES Hardware
76
Mangard Kai Schramm
91
Purpose Hardware
101
A Countermeasure to Reduce Side
242
Evaluation of DPA Countermeasures Using DualRail
255
it Hardware I
270
OSMolecular Realization of Rijndael
285
g SHA2 Hardware Implementations
298
Computing
311
stem 91
313
hannels III
324

iting the Elliptic Curve Method of Factoring
119
it Algorithms for Embedded Processors
134
stant Scalar Multiplication on Hyperelliptic Curve
148
An Update
160
hannels II
174
olution SideChannel Attack Using PhaseBased Waveform
187
illision Timing Attacks Against AES
201
Secure SBox Implementation Based on Fourier Transform
216
are Attacks and Countermeasures II
232
tack on Small RSA Public Exponent
339
are Attacks and Countermeasures III
369
ipping Method to Improve DPA Resistance of Quasi Delay
384
3d Design of Cryptographic Devices Resistant to Multiple
399
d Kulikowski Alexander Smirnov Alexander Taubin
412
Software Codesign of Elliptic Curve Cryptography
430
iplementation of Point Multiplication on Koblitz Curves
445
Index
451
Copyright

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