Cryptographic Hardware and Embedded Systems - CHES 2005: 7th International Workshop, Edinburgh, UK, August 29 - September 1, 2005, Proceedings

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Springer Science & Business Media, Aug 18, 2005 - Business & Economics - 458 pages
Thesearetheproceedingsofthe7thWorkshoponCryptographic Hardwareand EmbeddedSystems(CHES2005)heldinEdinburgh,ScotlandfromAugust29to September1,2005.TheCHESworkshophasbeensponsoredbytheInternational Association for Cryptologic Research (IACR) for the last two years. We received a total of 108 paper submissions for CHES 2005. The doub- blindreviewprocessinvolveda27-memberprogramcommittee anda largen- ber of external sub-referees. The review process concluded with a two week d- cussion process which resulted in 32 papers being selected for presentation. We are grateful to the program committee members and the external sub-referees for carrying out such an enormous task. Unfortunately, there were many strong papers that could not be included in the program due to a lack of space. We would like to thank all our colleagues who submitted papers to CHES 2005. In addition to regular presentations, there were three excellent invited talks given by Ross Anderson (University of Cambridge) on “What Identity Systems Can and Cannot Do”, by Thomas Wille (Philips Semiconductors Inc) on “- curity of Identi?cation Products: How to Manage”, and by Jim Ward (Trusted Computing Groupand IBM)on“TrustedComputing inEmbedded Systems”.It also included a rump session, chaired by Christof Paar, featuring informal talks on recent results.
 

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Contents

Resistance of Randomized Projective Coordinates Against Power Analysis
1
Templates as Master Keys
15
A Stochastic Model for Differential Side Channel Cryptanalysis
30
A New BabyStep GiantStep Algorithm and Some Applications to Cryptanalysis
47
Further Hidden Markov Model Cryptanalysis
61
EnergyEfficient Software Implementation of Long Integer Modular Arithmetic
75
Short Memory Scalar Multiplication on Koblitz Curves
91
HardwareSoftware Codesign for Hyperelliptic Curve Cryptography HECC on the 8051 μP
106
Comparison of Bit and Word Level Algorithms for Evaluating Unstructured Functions over Finite Rings
237
EM Analysis of Rijndael and ECC on a Wireless JavaBased PDA
250
Security Limits for Compromising Emanations
265
Security Evaluation Against Electromagnetic Analysis at Design Time
280
On SecondOrder Differential Power Analysis
293
Improved HigherOrder SideChannel Attacks with FPGA Experiments
309
Secure Data Management in Trusted Computing
324
Data Remanence in Flash Memory Devices
339

A Realizable Special Hardware Sieving Device for Factoring 1024Bit Integers
119
Scalable Hardware for Sparse Systems of Linear Equations with Applications to Integer Factorization
131
Design of Testable Random Bit Generators
147
Successfully Attacking Masked AES Hardware Implementations
157
DPAResistance Without Routing Constraints
172
Masking at Gate Level in the Presence of Glitches
187
Bipartite Modular Multiplication
201
Fast Truncated Multiplication for Cryptographic Applications
211
Using an RSA Accelerator for Modular Inversion
226
Prototype IC with WDDL and Differential Routing DPA Resistance Assessment
354
DPA Leakage Models for CMOS Logic Circuits
366
The Backend Duplication Method A LeakageProof PlaceandRoute Strategy for ASICs
383
Hardware Acceleration of the Tate Pairing in Characteristic Three
398
Efficient Hardware for the Tate Pairing Calculation in Characteristic Three
412
AES on FPGA from the Fastest to the Smallest
427
A Very Compact SBox for AES
441
Author Index
456
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