Current Sense Amplifiers for Embedded SRAM in High-Performance System-on-a-Chip Designs: For Embedded SRAM in High-Performance System-on-a-Chip Designs
System-on-a-chip (SoC) designs result in a wide range of high-complexity, high-value semiconductor products. As the technology scales towards smaller feature sizes and chips grow larger, a speed limitation arises due to an in creased RC delay associated with interconnection wires. Innovative circuit techniques are required to achieve the speed needed for high-performance signal processing. Current sensing is considered as a promising circuit class since it is inherently faster than conventional voltage sense amplifiers. How ever, especially in SRAM, current sensing has rarely been used so far. Practi cal implementations are challenging because they require sophisticated analog circuit techniques in a digital environment. The objective of this book is to provide a systematic and comprehen sive insight into current sensing techniques. Both theoretical and practical aspects are covered. Design guidelines are derived by systematic analysis of different circuit principles. Innovative concepts like compensation of the bit line multiplexer and auto-power-down will be explained based on theory and experimental results. The material will be interesting for design engineers in industry as well as researchers who want to learn about and apply current sensing techniques. The focus is on embedded SRAM but the material presented can be adapted to single-chip SRAM and to any other current-providing memory type as well. This includes emerging memory technologies like magnetic RAM (MRAM) and Ovonic Unified Memory (OUM). Moreover, it is also applicable to array like structures such as CMOS camera chips and to circuits for signal trans mission along highly capacitive busses.
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Current Sense Amplifiers for Embedded Sram in High-Performance System-On-a ...
No preview available - 2014
amplifier of Fig approximation AV/jv AVin AVout bias current I0 bitline capacitance bitline load bitline multiplexer bitline potential bitline voltage cascode cell current Chap circuit of Fig circuit simulation CMOS common-mode gain current sense amplifier current sensing circuit current sensing delay current sensing stage current transfer function curves dc voltage differential drain-source equations equivalent circuit feedback amplifier Figure frequency gain-bandwidth product gate implementation increases input current input dc input resistance input transistor input voltage difference iout latch latch-type sense amplifier load transistors memory cell MIN2 mismatch MOS transistor MRAM multiplexer compensation node noise margin offset voltage output voltage p-channel transistor parameters phase power-down precharge rmux Sect shown in Fig signal single-ended small-signal speed SRAM stability static step response switch transistor threshold voltage transconductance values of CBL VINDC voltage gain voltage sense amplifier voltage swing Vout Vref Vthn Vthp wordline yield zero
Page 157 - A High-Speed Sensing Scheme for IT Dynamic RAM's Utilizing the Clamped Bit-Line Sense Amplifier", IEEE J.
Page 153 - Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM's," IEEE Journal Of Solid-State Circuits, vol.
Page 156 - Katsuro Sasaki, Koichiro Ishibashi, Kiyotsugu Ueda, Kunihiro Komiyaji, Toshiaki Yamanaka, Naotaka Hashimoto, Hiroshi Toyoshima. Fumio Kojima, and Akihiro Shimizu, "A 7-ns 140-mW 1-Mb CMOS SRAM with Current Sense Amplifier," IEEE Journal of Solid-State Circuits, vol.
Page 153 - A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture,
Page 154 - A 295MHz CMOS 1M (x256) Embedded SRAM using Bi-directional Read/Write Shared Sense Amps and Self-Timed Pulsed Word-Line Drivers...
Page 154 - A 200 MHz 13 mm2 2-D DCT Macrocell Using Sense-Amplifying Pipeline Flip-Flop Scheme", IEEE Journal of Solid-State Circuits, vol.29 no.
Page 157 - Dual-vt SRAM cells with full-swing single-ended bit line sensing for high-performance on-chip cache in 0.