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MICROPROCESSOR BUS TRANSFERS
MEMORY SYSTEM DESIGN AND INTERFACING
INDUSTRY SYSTEM BUSES
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32 bits 32-bit memory address bus aligned asserted bank big-endian block buffer bus cycle bus master bus timing diagram byte lane byte sections cache controller cache line cache miss cacheable clock cycles configuration control signals coprocessor D-cache data bus data bus lines data cache data transfer decoding descriptor table doubleword DRAM DRAM controller example execution external fetch Futurebus hardware implemented indicates input clock cycle input pin Intel Intel Corporation interface interleaving interrupt Kbytes latch least significant least significant byte little-endian location 4N logical address space main memory memory chips microprocessor misaligned miss penalty miss rate mode module Motorola Multibus offset on-chip cache operand output physical address physical base address pipeline pointer port processor read cycle request RESET RISC segment descriptor segment registers shown in Figure significant byte SRAM stack strobe supervisor synchronous system bus task update vector number VMEbus word write cycle