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A Survey of High Performance Memory System Designs
An Analysis of Memory Reference Characteristics
Request Scheduling and Memory System Design 81
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8-way interleaved Access Processor ACKo ALA request algorithms array arrival order cache algorithms cache line cache memory cache miss cache words clock period contention-free memory system CPU cycles data cache datum decoupled architecture decoupled computation detect EP-First Execute Processor FCFS/1Q fetch request fetched operands FMRF with Data FMRF/1Q FMRF/RRF Free-Module-Request-First scheduling policy hardware queues I-unit IBM SYSTEM/360 instruction fetch integer interleaved memory system Interleaving Factors Scheduling LLL Loop load address request Load Data Queue memory access hazards memory bank busy memory conflicts Memory Controller memory model memory operation memory output memory requests memory transactions memory words Models Using LLL Module Controller multiplexing scheme Performance & Simulation PIPE architecture prefetched priority read request Read-After-Write access hazards Read-After-Write hazards Read-After-Write requests request arrival request queue Round-Robin sent SEQe SEQo sequence number shared variable simulation results storage store address requests store data store request Time-Division Total Simulation trace files trace-driven simulations