## Development of a processor array architecture for application to circuit simulation |

### What people are saying - Write a review

We haven't found any reviews in the usual places.

### Common terms and phrases

augmentation stage basic stage bits busses CAM load bus CAM's capabilities Chapter chip circuit simulation Communication Fragmentation communication lanes computation constraints Content Addressable Memory controller Data Dependency Graph data flow Data Structure DC analysis defined device model equations diagonal Division Algorithm double precision DPE array DPE implementation DPE's Figure floating point Forward Substitution Functional Block Diagram input iteration large number lead stage linear equations linear solution array linear solution step linearization array linearization step LU factorization mantissa Matrix ADD4 MFLOPS multi-cluster array nodal analysis node nonlinear number of clusters number of processors number of stages operands output packing algorithm performance pivot entry pivot row entry processing elements processor array architecture Processor Cluster Random Access Memory reciprocal relatively reordering result row segments scheduling single precision sparse sparse matrix SPICE2.G square root stage GEPE storage stored subprocess substitution steps task graph update operation update row utilization vector vector processor voltage