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A 2 Topological Routing Using Geometric Information
Race Detection for TwoPhase Systems
Tautology Checking Using CrossControllability
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Abstract algorithm analog analog circuits analysis applied approach assignment blocks Boolean cell channel chip circuit simulation clock CMOS components Computer Computer-Aided Design connected constraints cost cube defined delay density Design Automation Conference edge efficient equations equivalent error example fanout fault coverage fault simulation feedback vertex set floorplan function gate global routing graph heuristic hierarchical IEEE IEEE Trans implemented input interconnect iteration latch layout linear logic logic simulation logic synthesis machine matrix method minimize minimum module netlist nets node operations optimization output parameters partitioning path performance placement problem Proc procedure processors reduced router schedule segments sequence sequential circuits shown in Figure signal solution specification Steiner step switch-level synthesis Table techniques test pattern test vector testability Theorem tion topological transistor transition tree variables verification vertex vertices VLSI voltage waveform wiring