Digital Applications for CPLDs: A Lab Manual
Until now, digital logic or digital design courses have primarily focused on using fixed function TTL and CMOS integrated circuits as the vehicle for teaching principles of logic design. However, the digital design field has turned a corner; more and more, digital designs are being implemented in Programmable Logic Devices (PLDs). This unique lab manual addresses this new trend by focusing on PLDs as a vehicle for teaching the new digital paradigm.
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active-LOW Altera UP-1 board architecture body BIT_VECTOR ByteBlaster chip clock divider Concurrent Signal Assignment Connect CPLD Create a simulation Current File Default Symbol device dialog box digital-to-analog converter DIP switches Directories Download downto Dueck entity declaration EPROM FF FF FF File menu Function Pin Function Graphic Design File Hardware Description Language hexadecimal Hierarchy input and output INPUT VCC INPUT instructor Instructor's Initials Integrated Circuit JTAG latch logic LPM counter maj_vote majority vote circuit MAX+plus II File multiplexer Node Options Window Help OUTTUTT Pin Assignments Pin Function Pin PIN NAME PLD design ports and parameters programming pushbutton reset sawtooth select inputs Selected Signal Assignment serial seven-segment decoder seven-segment display shift register shown in Figure signal assignment statement STD_LOGIC STD_LOGIC_VECTOR switch debouncer synchronous truth table Tutorial UP-1 Circuit Board User Libraries VCC INPUT VCC vector VHDL file VHSIC waveforms wire Wire strippers