Digital Signal Processing with Field Programmable Gate Arrays
Field-Programmable Gate Arrays (FPGAs) are revolutionizing digital signal processing as novel FPGA families are replacing ASICs and PDSPs for front-end digital signal processing algorithms. So the efficient implementation of these algorithms is critical and is the main goal of this book. It starts with an overview of today's FPGA technology, devices, and tools for designing state-of-the-art DSP systems. A case study in the first chapter is the basis for more than 40 design examples throughout. The following chapters deal with computer arithmetic concepts, theory and the implementation of FIR and IIR filters, multirate digital signal processing systems, DFT and FFT algorithms, advanced algorithms with high future potential, and adaptive filters. Each chapter contains exercises. The VERILOG source code and a glossary are given in the appendices. This edition has a new chapter on microprocessors, new sections on special functions using MAC calls, intellectual property core design and arbitrary sampling rate converters, and over 100 new exercises.
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Finite Impulse Response FIR Digital Filters
Infinite Impulse Response IIR Digital Filters
Multirate Signal Processing
Fourier Transforms 343
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adaptive filter adder additional Altera approximation architecture arithmetic array assign B-spline begin bit width block Chebyshev clock cycles compiler complex component compute convolution CORDIC count Cyclone decoder defparam delay devices Digital Signal Processing DOWNTO END PROCESS error example ﬁlter filter bank filter coefficients FIR filter Flex floating-point FPGA frequency IEEE IEEE Transactions implementation input instantiation instruction INTEGER INTEGER RANGE iteration length LFSR LMS algorithm logic loop LSBs M4Ks mapping MatLab matrix memory MicroBlaze module MSBs Nios operands operation optimal output parameter PDSPs PicoBlaze pipeline stages polynomial port posedge clk processor quantization Quartus reg signed Registered Performance RISC sample sequence shown in Fig shows Signal Processing simulation speed stack machine STD_LOGIC step Table table_out transfer function transform twiddle factor values vector Verilog VHDL x_in Xilinx y_out zero