Digital System Design Using VHDL
This is a new text book introducing VHDL hardware description language & top down system design. The book emphasizes the difference between regular high level computer language & VHDL. As soon as VHDL constructs are introduced, readers are guided through a progressive series of examples to show the modeling techniques. More complex examples are introduced in later chapters to show the top down system design methodology. Distinguished features include: 89 examples of VHDL programming examples. Examples are available on diskette upon request. Exercises & problems at the end of chapters. Answer book available. MSI & SSI logic circuits modeling. Timing modeling & accuracy discussion. Corresponding behavioral, dataflow & structural models. Models of finite impulse response filter (FIR). Models of fast Fourier transform (FFT) hardware. Models of a simple 4-bit computer. Models of a SCSI communication protocol. Models of erasable programmable logic devices (EPLD). 1992 VHDL update in Appendix. DIGITAL SYSTEM DESIGN USING VHDL (ISBN 1-882819-00-4) $29.00. Digital System Design Using VHDL Examples Diskette (ISBN 1-882819-01-2) $15.00. To order: CorralTek, P.O. Box 2616, Salinas, CA 93902. Tel/FAX: (408) 484-1726.
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1 Design levels for digital systems
1 Entity and gate
26 other sections not shown
add_sub addr afterODEL algorithm architecture behavior array assert begin behavior architecture behavior model bit array bit_vector block BOOLEAN buffer butterfly clk'event and clk clock constant data flow model DATA OUT PHASE DB bus delay 400 ns delta cycle deskew delays device driver elsif end component end loop end process entity EPROM Example finite state machine FIR filter FPGA full adder gate level implementation IN_STR initiator input instantiation integer JEDEC logic value lup1 macrocell multiple next_state ODEL open collector operation output P_term package path hardware PORT MAP preset procedure r_bit r_byte RD8R resolution function resolved fun scsi delay SCSi initiator scsi target selection phase sensitivity list sequence sequential shown in Figure signal assignment statement ſº string literals target test bench triggered variable VHDL VHDL simulation W4 computer Xilinx ZZZZ