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ADDRESSING MODES 21
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Absolute Loader active address bits ASCII asserted backplane BDCOK H BDIN BDOUT BHALT BINIT BPOK H BRPLY BSYNC bus cycle bus driver bus error bus master Bus Receiver BWTBT byte cable chips circuit clock command configured connector console device control logic core memory DATOB decoded device address DMA device EIA interface flip-flop floppy disk functions gated goes low H goes H signal H9270 backplane Halt mode initialize input installed instruction interface interrupt request interrupt vector inverted jumpers line unit loaded LSI-11 processor LSI-11 system memory data register memory refresh microcode monitor normal octal operand option output Paragraph pins power supply power-up priority processor module produce PROM prompt character pulse read-only memory read/write memory reset resident memory responds RXDP selected sequence shown in Figure stack subroutine switch terminal trap user's device vector address voltage wire