Direct Conversion Receivers in Wide-Band Systems
Wide-band systems will be the next significant generation in wireless communications. Those include both wireless local area networks and cellular systems with a large coverage area. They will provide a higher data rate and access to internet and video services, for example. Although most of the data processing is performed digitally, also the requirements and possibilities to implement the analog part of the radio receiver will be different compared to the second-generation narrow-band receivers. Direct conversion architecture is a distinct candidate for wide-band systems because some non-idealities involved in baseband signal processing are significantly relaxed. The requirements and feasibility of direct conversion in wide-band systems are analyzed in this work. The main emphasis is on cellular systems based on direct sequence code division multiple access, but the same principles are generally valid in all receivers for different applications. The basic principles and design methods involved in receiver design are overviewed as well as the most common radio architectures. In a detailed analysis, the fundamental limitations of the direct conversion architecture are analyzed in wide-band signal processing. Especially, the effect of envelope distortion is characterized both with respect to the specific modulation and to the implementation of a downconversion mixer. Downconversion mixer is the key component in direct conversion because it transfers the radio frequency signal immediately down into the baseband after a relatively small gain at the preceding signal processing blocks, which do not provide filtering of the unwanted radio channels within the system band. Both switching mixers and subsampling mixers are analyzed. Direct Conversion Receivers in Wide-Band Systems consists of four different circuit implementations. A subharmonic sampler operating up to 2 GHz is implemented with a GaAs MESFET technology. The second IC is a CMOS low-noise amplifier with an optimized interface to a subsampling mixer. Two BiCMOS implementations of the wide-band direct conversion receiver are given. The first consists of four different chips: RF front-end, analog baseband circuitry and two analog-to-digital converters. In the second chip, all blocks from the low-noise amplifier to the A/D converters are placed on the same die. In that case, an excellent isolation is required between rail-to-rail clock signals and the sensitive RF input.
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Direct Conversion Receivers
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A/D converters amplifier amplitude architecture band bandwidth baseband BiCMOS bipolar blocks capacitance capacitor CDMA CDMA systems channel selection filter chip Circuits Conf clock CMOS component data rate dc offset defined demodulation desired channel despreading differential Digest of Technical Digital Signal Processing direct conversion receiver discussed downconversion mixers dynamic range Equation flicker noise frequency function given harmonic Hence IEEE IIP2 IIP3 image rejection impedance implementation Integrated Circuits interference intermodulation ISSCC ISSCC Digest linearity low-IF mismatch noise figure nonlinear number of bits on-chip operation optimization output parameters passband performance phase noise power consumption power levels preselection filter processing gain QPSK quadrature radio channel ratio RF front-end sampling second-order sensitivity shown in Figure signal levels signal path simulations single-chip Solid-State Circuits spectral stages structures subsampling mixer superheterodyne switching Technical Papers topology traffic channels transconductance transistor transmission transmitter typically unwanted WCDMA wide-band wireless