ESL Design and Verification: A Prescription for Electronic System Level Methodology
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Electronic System Level (ESL) design has mainstreamed it is now an established approach at most of the worlds leading system-on-chip (SoC) design companies and is being used increasingly in system design. From its genesis as an algorithm modeling methodology with no links to implementation, ESL is evolving into a set of complementary methodologies that enable embedded system design, verification and debug through to the hardware and software implementation of custom SoC, system-on-FPGA, system-on-board, and entire multi-board systems.
This book arises from experience the authors have gained from years of work as industry practitioners in the Electronic System Level design area; they have seen "SLD" or "ESL" go through many stages and false starts, and have observed that the shift in design methodologies to ESL is finally occurring. This is partly because of ESL technologies themselves are stabilizing on a useful set of languages being standardized (SystemC is the most notable), and use models are being identified that are beginning to get real adoption.
ESL DESIGN & VERIFICATION offers a true prescriptive guide to ESL that reviews its past and outlines the best practices of today.
Table of Contents
CHAPTER 1: WHAT IS ESL?
CHAPTER 2: TAXONOMY AND DEFINITIONS FOR THE ELECTRONIC SYSTEM LEVEL
CHAPTER 3: EVOLUTION OF ESL DEVELOPMENT
CHAPTER 4: WHAT ARE THE ENABLERS OF ESL?
CHAPTER 5: ESL FLOW
CHAPTER 6: SPECIFICATIONS AND MODELING
CHAPTER 7: PRE-PARTITIONING ANALYSIS
CHAPTER 8: PARTITIONING
CHAPTER 9: POST-PARTITIONING ANALYSIS AND DEBUG
CHAPTER 10: POST-PARTITIONING VERIFICATION
CHAPTER 11: HARDWARE IMPLEMENTATION
CHAPTER 12: SOFTWARE IMPLEMENTATION
CHAPTER 13: USE OF ESL FOR IMPLEMENTATION VERIFICATION
CHAPTER 14: RESEARCH, EMERGING AND FUTURE PROSPECTS
APPENDIX: LIST OF ACRONYMS
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Chapter 3 EVOLUTION OF ESL DEVELOPMENT
Chapter 4 WHAT ARE THE ENABLERS OF ESL?
Chapter 5 ESL FLOW
Chapter 6 SPECIFICATIONS AND MODELING
Chapter 7 PREPARTITIONING ANALYSIS
Chapter 8 PARTITIONING
Chapter 9 POSTPARTITIONING ANALYSIS AND DEBUG
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abstraction levels algorithm application approach architecture aspects behavioral synthesis blocks Chapter chip clock code coverage communication companies compiler complex components computation concurrency configurable constraints coprocessor cost coverage model cycle dataptr DCT_SIZE debug defined design flow design space discussed domain dynamic embedded systems engineers ESL design ESL flow ESL models example executable specification F/OSS FIFO Figure FPGA functional functional verification hardware hardware and software hardware design high-level HW/SW IEEE input interface JTAG language latency level of abstraction logic mapping memory methodology metrics multiple operating optimization OSCI partitioning performance platform possible post-partitioning pre-partitioning analysis problem processor protocol real-time requirements reuse scheduling silicon simulation software development standard static STMicroelectronics synthesis tool system design system-level SystemC SystemVerilog taxonomy techniques Tensilica tion Transaction-Level Modeling verification environment verification plan Verilog VHDL VLIW Xilinx
xxi. lappuse - Grant Martin Grant Martin is a chief scientist at Tensilica, Inc. in Santa Clara, California. Before that, Grant worked for Burroughs in Scotland for 6 years; Nortel/BNR in Canada for 10 years; and Cadence Design Systems for 9 years, eventually becoming a Cadence Fellow in their Labs. He received his Bachelor's and Master's degrees in Mathematics (Combinatorics and Optimization) from the University of Waterloo, Canada, in 1977 and 1978. Grant is a co-author of "Surviving the SOC Revolution: A Guide...