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ELECTRONIC PACKAGING DESIGN SPACE
IMPORTANT ASPECTS OF PACKAGE DESIGN
12 other sections not shown
A-I noise algorithm AUDiT average calculated capacitance ceramic chapter chip power circuits per chip clock skew CMOS components computed crosstalk cycle cycles per instruction density determined devices dielectric dielectric constant driver circuit Dual In-line Package electrical fanout Figure flip-chip free convection function fundamental limits gate glass-ceramic heat hybrid impedance input integrated circuit interconnect length line length linewidth logic material measurements microchannel cooling minimum multi-chip modules multi-chip package near-end crosstalk number of circuits off-chip on-chip delay optimization output package design package geometries package types packaging technology pads parameters partition performance Pin Grid Array plot problems propagation delay Rent's rule reserved for future response surface signal delay signal lines simulated annealing solder sub-elements substrate switching energy switching noise system package simulation temperature test chip test line test structures thermal resistance tion total number tradeoff values voltage width wiring space wiring tracks x-s plane