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Simple data transformations
Repetitive sampling techniques
8 other sections not shown
A/D converter accuracy additional hardware address bus address decoding circuit applications AR(n array artificial neurons AS(n backpropagation bytes cache memory cache RAM calculated choice between hardware clock control unit counter data pointers data sets described digital number digital signal processor DN_2 equation error distribution evaluated example execution feedforward FIFO given Gray code hardware and software hidden layer high speed IDAC input unit input waveform instructions interrupt service routine large number latch loop machine cycles main memory memory address decoding memory locations memory unit microprocessor microprocessor system module multiple neural network nominal frequency number of contacts operational amplifier output layer performed pipeline processing RAM address repetitive samples resistors sampling frequency scan sets of data shown in Fig significant bit software approach software implementation stored subroutine switched address decoding switched memory address transfer function truth table vector processor vectorized voltage waveform waveform zero