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Emerging Nanoelectronics: Life with and After CMOS, Volumes 1-3
Adrian M. Ionescu,Kaustav Banerjee
No preview available - 2005
applications architectures bias bulk buried oxide capacitance carbon nanotube carrier channel length circuits clock CMOS CMOS technology computing delay density depletion dielectric dopant doping double-gate drain electrical Electron Devices Meeting energy etch fabricated Figure film FinFET fluctuations frequency function gate length gate oxide gate voltage high-performance IEDM Tech IEEE IEEE Trans increase integration interface leakage current limit lithography logic memory metal gate microprocessors mobility molecular Moore's Law MOSFET nanoelectronics nanoscale NMOS node nology optical interconnects oxide thickness parameter performance Phys PMOS polysilicon potential power dissipation Proc quantum reduced resistance scaling semiconductor short channel effects shown in Fig shows SiGe SiGe layer signal silicide silicon SIMOX simulations source/drain strained strained silicon structure substrate subthreshold supply voltage switching technol temperature thermal thin threshold voltage tion transconductance transistor tunneling variations velocity VLSI wafer width wires