Error Control for Network-on-Chip Links
Springer Science & Business Media, Oct 9, 2011 - Technology & Engineering - 151 pages
This book provides readers with a comprehensive review of the state of the art in error control for Network on Chip (NOC) links. Coverage includes detailed description of key issues in NOC error control faced by circuit and system designers, as well as practical error control techniques to minimize the impact of these errors on system performance.
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Ampadu architecture BCH codes buffer burst errors CACs capacitive coupling CLK1 codec codes with type-II configurable error control coupling capacitance crosstalk crosstalk avoidance crosstalk coupling cyclic code DAP codes decoding process delay uncertainty error control codes error control schemes error correction capability error detection extended Hamming code extended Hamming product flit error rate Hamming distance Hamming product codes IEEE Trans implementation increases Integr Circuits interleaving Large Scale Integr layer linear block code link delay link energy consumption link length link swing voltage method minimum Hamming distance network-on-chip noise environments number of wires on-chip communication on-chip interconnects operating mode-(b packet parity bit parity check bits parity check matrix permanent errors reduce reliability of on-chip repeater insertion residual flit error retransmission router Scale Integr VLSI Shanbhag shown in Fig skewed transitions Springer Science+Business Media switching syndrome syndrome decoder technology scales Trans Very Large type-II HARQ virtual channels VLSI