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Description of the Dispatch Stack
Enhancements to the Dispatch Stack
Conclusions and Future Directions
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2P 4P FP algorithm architecture benchmarks branch instructions branch outcomes concurrency extraction concurrent execution condition code conditional branch configurations content addressable data dependencies delays dependency counters dependency information destination register detection Dispatch Stack DStinfanf dynamic code scheduling dynamic scheduling EBUS elimination enhancing execution resources Execution Unit Fetch Count fetch phase fields Figure floating point FP modes FPIPE hand-compilation hardware immediate operand implementation instruction issuing mechanism instruction set instruction window instructions per cycle IP 2P 4P issued per cycle issuing instructions loop loop unrolling machine memory access multiple functional unit multiple instructions non-sequential number of instructions parallel issuing modes partial order peephole optimizations performance pipelined Precedence Count Memory PtEBUS PtFPIPE PtPARA PtXBAR redundant computations redundant load register allocation register renaming Section sequential serial execution stream shadow effects simulator source registers speedups static scheduling Table techniques Throughput tion Tjaden transitive closure update phase useless assignments values