FPGA Design: Best Practices for Team-based Design
Springer Science & Business Media, Jul 23, 2010 - Technology & Engineering - 151 pages
In August of 2006, an engineering VP from one of Altera’s customers approached Misha Burich, VP of Engineering at Altera, asking for help in reliably being able to predict the cost, schedule and quality of system designs reliant on FPGA designs. At this time, I was responsible for defining the design flow requirements for the Altera design software and was tasked with investigating this further. As I worked with the customer to understand what worked and what did not work reliably in their FPGA design process, I noted that this problem was not unique to this one customer. The characteristics of the problem are shared by many Corporations that implement designs in FPGAs. The Corporation has many design teams at different locations and the success of the FPGA projects vary between the teams. There is a wide range of design experience across the teams. There is no working process for sharing design blocks between engineering teams. As I analyzed the data that I had received from hundreds of customer visits in the past, I noticed that design reuse among engineering teams was a challenge. I also noticed that many of the design teams at the same Companies and even within the same design team used different design methodologies. Altera had recently solved this problem as part of its own FPGA design software and IP development process.
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Altera analysis ASIC Best Practices board design challenges changes clock closure code coverage complete constraints coverage creating debug debug logic delay design blocks design cycle design environment design flow design methodology design reuse design team documentation DSP blocks EDA tools enable ensure files floorplan FPGA design software FPGA devices FPGA family FPGA vendor software functional verification hardware impact implementation in-system debug incremental compilation input interface IP core JTAG Logic Analyzer module netlist operation optimizations options output partitioning performance pin assignments place and route placement power supply Practices for Team-based problem Quartus recommended Register Address Map regression test requirements reset reusable RTL code RTL design scenario Signal Integrity soft processor specification Springer Science+Business Media Static timing analysis synchronous synthesis tools SystemVerilog Team-based Design techniques testbench toggle rate top-level transceiver Verilog version control VHDL