Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream

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Manfred Glesner, Peter Zipf, Michel Renovell
Springer Science & Business Media, Aug 21, 2002 - Computers - 1192 pages
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This book is the proceedings volume of the 12th International Conference on Field-ProgrammableLogicandApplications(FPL)heldonSeptember2 4,2002. The conference was hosted by the Laboratoired Informatique, de Robotique et de Micro electronique de Montpellier (LIRMM), France. The FPL conference covered areas like recon?gurable logic and recon?gurable computing, as well as their application in various areas like DSP, communication and cryptography. Its subtitle Recon?gurable Computing Is Going Mainstream emphasizes the extensive role recon?gurablelogic has started to play. The annual FPL series is the oldest international conference in the world covering con?gware and all its aspects (also see: http: //www.fpl.org). It was foundedin1991atOxfordUniversity(UK)andistwoyearsolderthanitstwo most important competitors, which usually take place in Monterey and Napa. FPLhasbeenheldinOxford(threetimes), Vienna, Prague, Darmstadt, London, Tallinn, Glasgow, Villach, and Belfast. It brings together experts, users, and newcomers from industry and academia in an informal, social, and productive atmosphere that encourages stimulating and pro?table interaction between the participants. Covered topics. The scope of this conference has been substantially - tended over the past years and today also covers evolvable and adaptable s- tems, coarse-grainrecon?gurable(sub)systems, theirsynthesismethods and- plications, andtheirindispensableroleinSystem-on-a-Chip(SoC)development, aswellasrecon?gurablecomputing(RC)asanemergingnewparadigm, thre- ening to shakethe generalfoundations ofcomputer science: computing in space vs. computing in time. The application of ?eld-programmable logic in di?- ent areas has gained increasing importance also, and the number of according submissions has grown."
 

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Contents

The Age of Adaptive Computing Is Here
1
Disruptive Trends by DataStreamBased Computing
4
Multithreading for LogicCentric Systems
5
Fast Prototyping with Cooperation of Simulation and Emulation
15
Lessons and Challenges from the Digital TV Design Prototyping Project
26
Implementing Asynchronous Circuits on LUT Based FGAs
36
A Technique for FPGS Synthesis Driven by Automatic Source Code Analysis and Transformations
47
Flexible Routing Architecture Generation for DomainSpecific Reconfigurable Subsystems
59
An Enhanced POLIS Framework for Fast Exploration and Implementation of IO Subsystems on CSoC Platforms
677
An Operating System for Reconfiguring Computing
687
Efficient Metacomputation Using SelfReconfiguration
698
An FPGA Coprocessor for RealTime Visual Tracking
710
Implementation of 3D Adaptive LUM Smoother in Reconfigurable Hardware
720
Custom Coprocessor Based Matrix Algorithms for Image and Signal Processing
730
Parallel FPGA Implementation of the Split and Merge Discrete Wavelet Transform
740
Fully Parameterizable Elliptic Curve Cryptography Processor over GF2m
750

A Portable Adaptive Computing Engine for Real Time Applications
69
FieldProgrammble Custom Computing Machines A Taxdonomy
79
Embedded Reconfigurable Logic Core for DSP Applications
89
Application to the DVB Standard
102
FPGA QAM Demodulator Design
112
Analytical Framework for Switch Block Design
122
Modular FabricSpecific Synthesis for Programmable Architectures
132
On Optimum Designs of Universal Switch Blocks
142
Improved Functional Simulation of Dynamically Reconfigurable Logic
152
An Application of JBits Technology
162
Dynamic Reconfiguration in Mobile Systems
171
Using PARBIT to Implement Partial RunTime Reconfigurable Systems
182
Multiplierless Realization of a Polyphase Filter Using LUTbased FPGAs
192
Speech Recognition on an FPGA Using Discrete and Continous Hidden Markov Models
202
FPGA Implementation of the Wavelet Packet Transform for High Speed Communications
212
A Method for Implementing BitSerial Finite Impulse Response Digital Filters in FPGAs Using JBits
222
Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices
232
Rapid and Reliable Routability Estimation for FPGAs
242
Integrated Iterative Approach to FPGA Placement
253
A DistributedMemory Parallel Routing Algorithm for FPGAs
263
HighLevel Partitioning of Digital Systems Based on Dynamically Reconfigurable Devices
271
High Speed Homology Search Using RunTime Reconfigurable
281
Partially Reconfigurable Cores for Xilinx Virtex
292
Online Defragmentation for RunTime Partially Reconfigurable FPGAs
302
A Flexible Power Model for FPGAs
312
A Clocking Technique with Power Savings in VirtexBased Pipelined Designs
322
Energy Evaluation on a Reconfigurable MultimediaOriented Wireless Sensor
332
A Tool for Activity Estimation in FPGAs
340
FSM Decomposition for Low Power in FPGA
350
Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search
360
A PrologBased Hardware Development Environment
370
Fly A Modifiable Hardware Compiler
381
Challenges and Opportunities for FPGA Platforms
391
Design and Implementation of FPGA Circuits for High Speed Network Monitors
393
Towards Gigabit Rate Network Instrusion Detection Technology
404
Fast SiGe HBT BiCMOS FPGAs with New Architecture and Power Saving Techniques
414
A FloatingGate Approach
424
A Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the Model
434
A Framework for Teaching ReConfigurable Architectures in Student Projects
444
Specialized Hardware for Deep Network Packet Filtering
452
Implementation of a Successive Erasure BCH 1676 Decoder and Performance Simulation by Rapid Prototyping
462
Fast RNS FPLbased Communications Receiver Design and Implementation
472
A Reconfigurable Architecture for Video Image Processing
482
Implementing the Discrete Cosine Transform Using the Xilinx Virtex FPGA
492
Implementation of the JPEG 2000 Standard on a Virtex 1000 FPGA
503
Small MultiplierBased Multiplication and Division Operators for VirtexII Devices
513
Automating Customisation of FloatingP oint Designs
523
EnergyEfficient Matrix Multiplication on FPGAs
534
RunTime Adaptive Flexible Instruction Processors
545
DARP A Digital Audio Reconfigurable Processors
556
SystemLevel Modelling for Performance Estimation of Reonfiguration Coprocessors
567
An FPGA Based SHA256 Processor
577
Handling FPGA Faults and Configuration Sequencing Using a Hardware Extension
586
On the Set of Target Path Delay Faults in Sequential Subcircuits of LUTbased FPGAs
596
SimulationBased Analysis of SEU Effects on SRAMBased FPGAs
607
Exploiting Reconfigurability for Effective Testing of Delay Faults in Sequential Subcircuits of LUTbased FPGAs
616
Logarithmic Number System and FloatingPoint Arithmetics on FPGA
627
Novel Optimizations for Hardware FloatingPoint Units in a Modern FPGA Architecture
637
Morphable Multipliers
647
A Library of Parameterized FloatingPoint Modules and Their Use
657
Wordlength as an Architectural Parameter for Reconfigurable Computing Devices
667
678 Gigabits per Second Implementation of the IDEA Cryptographic Algorithm
760
Rijndael Cryptographic Engine on the UltraSONIC Reconfigurable Platform
770
First FPGA Implementation
780
Creating a World of Smart Reconfigurable Devices
790
Interconnection Networks Enable FineGrain Dynamic Multitasking on FPGAs
795
Multitasking Hardware on the SLAAC1V Reconfigurable Computing System
806
An Analysis of Conceived Performance
816
An FPGA Implementation of a Multicomparand Multisearch Associative Processor
826
Time Flexibility Tradeoff
836
An FPGA Implementation of the Linear Cryptanalysis
845
Compiling ApplicationSpecific Hardware
853
A C Compiler with Temporal Partitioning for the PACTXPP Architecture
864
A Synthesizing Compiler for FPGAs
875
Practical Considerations in the Synthesis of High Performance Digital Filters for Implementation on FPGAs
886
Low Power High Speed Algebraic Integer Frequency Sampling Filters FPLDs
897
High Performance Quadrature Digital Mixers for FPGAs
905
Efficient Multicontext Graph Processors
915
Scalable Implementation of the Discrete Element Method on a Reconfigurable Computing Platform
925
On Computing TransitiveClosure Equivalence Sets Using a Hybrid GADP Approach
935
A Processor Core for Reactive Embedded Applications
945
Factors Influencing the Performance of a CPURFU Hybrid Architecture
955
Implementing Converters in FPLD
966
A Quantitative Understanding of the Performance of Reconfigurable Coprocessors
976
Integration of Reconfigurable Hardware into SystemLevel Design
987
A Retargetable Macro Generation Method for the Evaluation of Repetitive Configurable Architectures
997
The Integration of SystemC and HardwareAssisted Verification
1007
Using Design Hierarchy to Improve Quality of Results in FPGAs
1017
Architecture Design of a Reconfigurable Multiplier for Flexible CoarseGrain Implementations
1027
A General Hardware Design Model for Multicontext FPGAs
1037
Dynamically Reconfigurable Hardware A New Perspective for Neural Network Implementations
1048
A Compilation Framework for a Dynamically Reconfigurable Architecture
1058
Data Dependent Circuit for Subgraph Isomorphism Problem
1068
Exploration of Design Space in ECDSA
1072
2D and 3D Computer Graphics Algorithms underMORPHOSYS
1076
A HIPERLAN2 IEEE 80211a Reconfigurable SystemonChip
1080
An FPGA Implementation of the TOTEM Parallel Processor
1084
RealTime Medical Diagnosis on a Multiple FPGAbased System
1088
Threshold ElementBased Symmetric Function Generators and Their Functional Extension
1092
Hardware Implementation of a Multiuser Detection Scheme Based on Recurrent Neural Networks
1097
Building Custom FIR Filters Using System Generator
1101
SoC Based Low Cost Design of Digital Audio Broadcasting Transport Network Applications
1105
Dynamic Constant Coefficient Convolvers Implemented in FPGAs
1110
An FPGAbased Interactive Volume Rendering System
1114
A Reconfigurable Network Interface for Cluster Computing
1118
General Purpose Prototyping Platform for DataProcessor Research and Development
1122
High Speed Computation of Three Dimensional Cellular Automata with FPGA
1126
SOPCbased Embedded Smart Strain Gage Sensor
1131
Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications
1135
An FPGAbased Node Controller for a High Capacity WDM Optical Packet Network
1139
FPGA and Mixed FPGADSP Implementations of Electrical Drive Algorithms
1144
Image Registration of RealTime Broadcast Video Using the UltraSONIC Reconfigurable Computer
1148
A Novel Watermarking Technique for LUT Based FPGA Designs
1152
Implementing CSAT Local Search on FPGAs
1156
A Reconfigurable Processor Architecture
1160
A Reconfigurable SystemonChipBased Fast EDM Process Monitor
1164
Gene Matching Using JBits
1168
Massively ParallelReconfigurable Emulation Model for the Dalgorithm
1172
A PlacementRouting Approach for FPGA Accelerators
1177
Author Index
1183
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