Field-Programmable Logic and Applications: 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001 Proceedings

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Springer Science & Business Media, Aug 15, 2001 - Computers - 665 pages
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This book contains all of the papers presented at the 11th International C- ference on Field Programmable Logic and Applications (FPL 2001), hosted by The Queen's University of Belfast, Northern Ireland,27-29 August 2001. The annual FPL event is the longest-standing international conference covering p- grammable logic, recon?gurable computing, and related matters. It was founded in 1991, and has been held in Darmstadt, Glasgow, London, Oxford (thrice), Prague, Tallinn, Vienna, and Villach. FPL brings together experts, users, and newcomers from industry and academia, in an informal and convivial atmosphere that encourages stimulating and productive interaction between participants. The size of the FPL conference has been growing rapidly, the number of participants increasing from 144 in 1999 to 240 in 2000. The number of papers submitted in 2001 was in line with the previous year, and our goal for 2001 was to sustain the growth in participation. The 117 submitted papers came from 24 di?erent countries: USA (26), UK (24), Germany (14), Spain (12), Japan (7), France (4), Greece and Ireland (3 each), Belgium, Canada, Czech Republic, Finland, Italy, The Netherlands, Poland, and Switzerland (2 each), and Austria, Belarus, Brazil, Iran, Mexico, Portugal, South Africa, and Sweden (1 each). This illustrates the position of FPL as a genuinely international event, with by far the largest number of submissions of any conference in this ?eld. As in previous years, each submitted paper was subjected to thorough reviewing. As a result, 56 regular papers and 15 posters were accepted for presentation. Another three keynote papers were invited. We thank all the authors who submitted papers, and also thank the members of the program committee and the additional referees who carefully reviewed the submissions.
 

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Contents

Technology Trends and Adaptive Computing
1
Prototyping Framework for Reconfigurable Processors
6
An Emulator for Exploring RaPiD Configurable Computing Architectures
17
A New Placement Method for Direct Mapping into LUTBased FPGAs
27
fGREP Fast Generic Routing Demand Estimation for Placed FPGA Circuits
37
Macrocell Architectures for Product Term Embedded Memory Arrays
48
Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAs
59
Memory Synthesis for FPGABased Reconfigurable Computers
70
A Music Synthesizer on FPGA
377
Motivation from a FullRate Specific Design to a DSP Core Approach for GSM Vocoders
388
Loop Tiling for Reconfigurable Accelerators
398
A Dynamically Reconfigurable Architecture for Embedded Systems
409
A nBit Reconfigurable Scalar Quantiser
420
Real Time Morphological Image Contrast Enhancement in Virtex FPGA
430
Demonstrating RealTime JPEG Image CompressionDecompression Using Standard Component IP Cores on a Programmable Logic Based Platform f...
441
Design and Implementation of an Accelerated Gabor Filter Bank Using Parallel Hardware
451

Implementing a Hidden Markov Model Speech Recognition System in Programmable Logic
81
Implementation of Normalised RLS Lattice on Virtex
91
Accelerating Matrix Product on Reconfigurable Hardware for Signal Processing
101
Static ProfileDriven Compilation for FPGAs
112
Synthesizing RTL Hardware from Java Byte Codes
123
From Behavioral Specification to MultiFPGAPrototype
133
Secure Configuration of Field Programmable Gate Arrays
142
SingleChip FPGA Implementation of the Advanced Encryption Standard Algorithm
152
JBits TM Implementations of the Advanced Encryption Standard Rijndael
162
TaskParallel Programming of Reconfigurable Systems
172
ChipBased Reconfigurable Task Management
182
Configuration Caching and Swapping
192
Multiple Stereo Matching Using an Extended Architecture
203
Implementation of a NURBS to Bézier Conversor with Constant Latency
213
Reconfigurable FrameGrabber for RealTime Automated Visual Inspection RTAVI Systems
223
Processing Models for the Next Generation Network
232
Tightly Integrated Placement and Routing for FPGAs
233
A Tool for the Simultaneous Placement and Detailed Routing of GateArrays
243
Reconfigurable Router Modules Using Network Protocol Wrappers
254
Development of a Design Framework for PlatformIndependent Networked Reconfiguration of Software and Hardware
264
The MOLEN ρµCoded Processor
275
RunTime Optimized Reconfiguration Using Instruction Forecasting
286
A Template for Reconfigurable Instruction Set Processors
296
Evaluation of an FPGA Implementation of the Discrete Element Method
306
RunTime Performance Optimization of an FPGABased Deduction Engine for SAT Solvers
315
A Reconfigurable Embedded Input Device for Kinetically Challenged Persons
326
Bubble Partitioning for LUTBased Sequential Circuits
336
Rapid Construction of Partial Configuration Datastreams from HighLevel Constructs Using JBits
346
Placing Routing and Editing Virtual FPGAs
357
Virtex Implementation of Pipelined Adaptive LMS Predictor in Electronic Support Measures Receiver
367
Past Present and Future Predictions
461
Dynamically Reconfigurable Cores
462
Reconfigurable Breakpoints for Codebug
473
Using DesignLevel Scan to Improve FPGA Design Observability and Controllability for Functional Verification
483
FPGABased Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits
493
A Generic Library for Adaptive Computing Environments
503
Generative Development System for FPGA Processors with Active Components
513
Compilation Increasing the Scheduling Scope for MultimemoryFPGABased Custom Computing Machines
523
System Level Tools for DSP in FPGAs
534
Parameterized Function Evaluation for FPGAs
544
Efficient Constant Coefficient Multiplication Using Advanced FPGA Architectures
555
A DigitSerial Structure for Reconfigurable Multipliers
565
FPGA Resource Reduction Through Truncated Multiplication
574
Efficient Mapping of Presynthesized IPCores onto Dynamically Reconfigurable Array Architectures
584
An FPGABased Syntactic Parser for RealLife Almost Unrestricted ContextFree Grammars
590
A Reconfigurable and Evolutionary Computing Approach
595
An Approach to RealTime Visualization of PIV Method with FPGA
601
FPGABased Discrete Wavelet Transforms System
607
A ProASICBased 200 Mbytess FullDuplex Lossless Data Compressor
613
RHW
618
Initial Analysis of the Proteus Architecture
623
Building Asynchronous Circuits with JBits
628
Case Study of Integration of Reconfigurable Logic as a Coprocessor into a SCICluster under RTLinux
633
A Reconfigurable Approach to Packet Filtering
638
FPGABased Modelling Unit for High Speed Lossless Arithmetic Coding
643
A Data Reuse Based Compiler Optimization for FPGAs
648
Dijkstras Shortest Path Routing Algorithm in Reconfigurable Hardware
653
A System on Chip for Power Line Communications According to European Home Systems Specifications
658
Author Index
663
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About the author (2001)

ROGER WOODS is Professor of German at the University of Nottingham.

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