Field-Programmable Logic and Applications. The Roadmap to Reconfigurable Computing: 10th International Conference, FPL 2000 Villach, Austria, August 27-30, 2000 Proceedings
Reiner W. Hartenstein, Herbert Grünbacher
Springer, Oct 2, 2000 - Computers - 856 pages
This book constitues the refereed proceedings of the 10th International Conference on Field-Programmable Logic and Applications, FPL 2000, held in Villach, Austria in August 2000. The 64 revised full papers presented together with eight invited contributions and 21 short papers were carefully reviewed and selected from a total of 131 submissions. The book offers topical sections on network processors, prototyping, dynamic reconfigurability, technology mapping/routing and placement, biologically inspired methods, mobile communciation, design space exploration, optimization, architectures, methodology and technology, compilation, applications, and miscellaneous.
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adder algorithm application architecture Berlin Heidelberg 2000 bits buffer cache chip circuit CLBs clock cycle communication components configuration connected constraints context context switch coprocessor device dynamically reconfigurable embedded Embedded Systems encoding evolvable hardware execution Field Programmable Field-Programmable Gate Arrays floorplan FPGA function Gate Arrays genetic algorithm graph Handel-C hardware Hartenstein and H IEEE implementation input interconnect interface latency LNCS logic cell mapping memory microprocessor module multiplexer multiplier netlist neuron nodes operation optimal output parallel partitioning performance pipelined placement port problem Proc processing processor programmable logic programmable logic device prototyping R.W. Hartenstein reconfigurable computing routing run-time scheduling Section serial shown in Figure signal simulated annealing simulation solution Springer-Verlag Berlin Heidelberg SRAM stream structure subgraph switch synthesis Table target task techniques variables vector Verilog VHDL Virtex VLSI Xilinx