Field-Programmable Logic and Applications. The Roadmap to Reconfigurable Computing: 10th International Conference, FPL 2000 Villach, Austria, August 27-30, 2000 Proceedings

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This book is the proceedings volume of the 10th International Conference on Field Programmable Logic and its Applications (FPL), held August 27 30, 2000 in Villach, Austria, which covered areas like reconfigurable logic (RL), reconfigurable computing (RC), and its applications, and all other aspects. Its subtitle "The Roadmap to Reconfigurable Computing" reminds us, that we are currently witnessing the runaway of a breakthrough. The annual FPL series is the eldest international conference in the world covering configware and all its aspects. It was founded 1991 at Oxford University (UK) and is 2 years older than its two most important competitors usually taking place at Monterey and Napa. FPL has been held at Oxford, Vienna, Prague, Darmstadt, London, Tallinn, and Glasgow (also see: http://www. fpl. uni kl. de/FPL/). The New Case for Reconfigurable Platforms: Converging Media. Indicated by palmtops, smart mobile phones, many other portables, and consumer electronics, media such as voice, sound, video, TV, wireless, cable, telephone, and Internet continue to converge. This creates new opportunities and even necessities for reconfigurable platform usage. The new converged media require high volume, flexible, multi purpose, multi standard, low power products adaptable to support evolving standards, emerging new standards, field upgrades, bug fixes, and, to meet the needs of a growing number of different kinds of services offered to zillions of individual subscribers preferring different media mixes.
 

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Contents

The Rising Wave of Field Programmability
1
Tightly Integrated Design Space Exploration with Spatial and Temporal Partitioning in SPARCS
7
A Dynamically Reconfigurable FPGABased Content Addressable Memory for Internet Protocol Characterization
19
A Compiler Directed Approach to Hiding Configuration Latency in Chameleon Processors
29
Reconfigurable Network Processors Based on Field Programmable System Level Integrated Circuits
39
Internet Connected FPL
48
Field Programmable Communication Emulation and Optimization for Embedded System Design
58
Industrial and Custom Prototyping Solutions
68
A Multinode Dynamic Reconfigurable Computing System with Distributed Reconfiguration Controller
469
A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems
475
A CORDIC Arctangent FPGA Implementation for a HighSpeed 3DCamera System
485
Preliminary Findings
495
Security Upgrade of Existing ISDN Devices by Using Reconfigurable Logic
505
The Fastest Multiplier on FPGAs with Redundant Binary Representation
515
HighLevel Area and Performance Estimation of Hardware Building Blocks on FPGAs
525
Balancing Logic Utilization and Area Efficiency in FPGAs
535

FPGABased Prototyping for Product Definition
78
Implementation of Virtual Circuits by Means of the FIPSOC Devices
87
Static and Dynamic Reconfigurable Designs for a 2D ShapeAdaptive DCT
96
A SelfReconfigurable Gate Array Architecture
106
Multitasking on FPGA Coprocessors
121
Design Visualisation for Dynamically Reconfigurable Systems
131
Verification of Dynamically Reconfigurable Logic
141
Design of a Fault Tolerant FPGA
151
RealTime Face Detection on a Configurable Hardware System
157
Multifunctional Programmable SingleBoard CAN Monitoring Module
163
SelfTesting of Linear Segments in UserProgrammed FPGAs
169
Implementing a Fieldbus Interface Using a FPGA
175
AreaOptimized Technology Mapping for Hybrid FPGAs
181
Direct Mapping of Arbitrary Components into LUTBased FPGAs
191
Efficient Embedding of Partitioned Circuits onto MultiFPGA Boards
201
A Placement Algorithm for FPGA Designs with Multiple IO Standards
211
A Mapping Methodology for Code Trees onto LUTBased FPGAs
221
Possibilities and Limitations of Applying Evolvable Hardware to RealWorld Applications
230
A Coprocessor System with a Virtex FPGA for Evolutionary Computation
240
System Design with Genetic Algorithms
250
Implementing Kak Neural Networks on a Reconfigurable Computing Platform
260
Compact Spiking Neural Network Implementation in FPGA
270
Silicon Platforms for the Next Generation Wireless Systems What Role Does Reconfigurable Hardware Play?
277
Spanning the Electronic Microfluidic and Biomolecular Domains
286
A Specific Test Methodology for Symmetric SRAMBased FPGAs
300
A Dynamically Reconfigurable Architecture for Future Mobile Communication Applications
312
Fast Carrier and Phase Synchronization Units for Digital Receivers Based on Reconfigurable Logic
322
Software Radio Reconfigurable Hardware System SHaRe
332
Discrete Wavelet Transform
342
Partial RunTime Reconfiguration Using JRTR
352
A Combined Approach to HighLevel Synthesis for Dynamically Reconfigurable Systems
361
A Hybrid Prototyping Platform for Dynamically Recofigurable Designs
371
Task Rearrangement on Partially Reconfigurable FPGAs with Restricted Buffer
379
Generation of Design Suggestions for CoarseGrain Reconfigurable Architectures
389
Mapping of DSP Algorithms on Field Programmable Function Arrays
400
On Availability of BitNarrow Operations in GeneralPurpose Applications
412
A Comparison of FPGA Implementations of BitLevel and WordLevel Matrix Multipliers
422
A New Floorplanning Method for FPGA Architectural Research
432
Efficient SelfReconfigurable Implementations Using Onchip Memory
443
Design and Implementation of an XC6216 FPGA Model in Verilog
449
Reusable DSP Functions in FPGAs
456
A Parallel Pipelined SAT Solver for FPGAs
462
Performance Penalty for Fault Tolerance in Roving STARs
545
Optimum Functional Decomposition for LUTBased FPGA Synthesis
555
Optimization of RunTime Reconfigurable Embedded Systems
565
Its FPL Jim But Not as We Know It Opportunities for the New Commercial Architectures
575
New Activities in Asia
585
ObjectOriented Programming of Stream Architectures Using PAMBlox
595
Stream Computations Organized for Reconfigurable Execution SCORE
605
Memory Access Schemes for Configurable Processors
615
Generating Addresses for Multidimensional Array Access in FPGA Onchip Memory
626
MultipleWordlength Resource Binding
646
Automatic Temporal Floorplanning with Guaranteed Solution Feasibility
656
A Threshold LogicBased Reconfigurable Logic Element with a New Programming Technology
665
Exploiting Reconfigurability for Effective Detection of Delay Faults in LUTBased FPGAs
675
Dataflow Partitioning and Scheduling Algorithms for WASMII a Virtual Hardware
685
An Example of Automatic HWSW Partitioning and Synthesis
695
Behavioural Language Compilation with Virtual Hardware Management
707
Synthesis and Implementation of RAMBased Finite State Machines in FPGAs
718
Evaluation of Accelerator Designs for Subgraph Isomorphism Problem
729
The Implementation of Synchronous Dataflow Graphs Using Reconfigurable Hardware
739
Multiplexer Based Reconfiguration for Virtex Multipliers
749
Efficient Building of Word Recognizer in FPGAs for TermDocument Matrices Construction
759
Reconfigurable Computing between Classifications and Metrics The Approach of SpaceTimeScheduling
769
FPGA Implementation of a Prototype WDM OnLine Scheduler
773
An FPGA Based Scheduling Coprocessor for Dynamic Priority Scheduling in Hard RealTime Systems
777
Formal Verification of a Reconfigurable Microprocessor
781
The Role of the Embedded Memories in the Implementation of Artificial Neural Networks
785
Programmable System Level Integration Brings Systemon Chip Design to the Desktop
789
On Applying Software Development Best Practice to FPGAs in SafetyCritical Systems
793
A Routing Tool for RunTime Reconfiguration
797
High Speed Computation of Lattice Gas Automata with FPGA
801
An Implementation of Longest Prefix Matching for IP Router on Plastic Cell Architecture
805
FPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational Numbers
810
Toward Uniform Approach to Design of Evolvable Hardware Based Systems
814
Educational Programmable Hardware Prototyping and Verification System
818
A Stream Processor Architecture Based on the Configurable CEPRAS
822
An Innovative Approach to Couple EDA Tools with Reconfigurable Hardware
826
FPL Curriculum at Tallinn Technical University
830
The Modular Architecture of SYNTHUP FPGA Based PCI Board for RealTime Sound Synthesis and Digital Signal Processing
834
A Rapid Prototyping Environment for Microprocessor Based SystemonChips and Its Application to the Development of a Network Processor
838
Author Index
853
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